MEMS Package Design with Vertical Stacked Die Interconnect
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Solution Overview
Problem
Current semiconductor device packaging technologies face challenges in achieving compact, efficient electrical interconnection while allowing external stimuli to reach sensors, particularly in MEMS devices like microphones, due to space constraints and limitations in package size reduction.
Innovation Solution
The implementation of a semiconductor package design that includes a MEMS semiconductor die mounted over an embedded wafer level ball grid array (eWLB) with prefabricated modular interconnect units, which allows for vertical interconnection and reduces package size by stacking semiconductor dies and using prefabricated modular interconnect units for cost-effective and flexible manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional semiconductor device packaging is used, then electrical interconnection is achieved, but package size and footprint are larger than desired
Solution Approach 1:
The patent transitions from planar horizontal interconnection to vertical three-dimensional interconnection by stacking semiconductor dies and using through-silicon vias (TSVs) for electrical connection. This dimensional change allows multiple devices to be integrated in the vertical direction, significantly reducing the package footprint while maintaining complex electrical interconnection capabilities.
Solution Approach 2:
The patent implements nested integration by placing one semiconductor die directly on top of another, with lower dies serving as support structures for upper dies. This nesting approach maximizes space utilization and reduces the overall package area while enabling complex interconnections through vertical stacking.
2Adaptability or versatility
If sensor cavities are provided for external stimuli access, then sensor functionality is enabled, but package size and space for interconnection are reduced
Solution Approach 1:
The patent resolves the space conflict by moving electrical interconnection from the horizontal plane to the vertical dimension through TSVs and stacked die configuration. This allows sensor cavities to access external stimuli from the top surface while electrical connections are routed vertically through the substrate, eliminating spatial conflict between sensor access and interconnection requirements.
3Area of stationary object
If multiple semiconductor dies are integrated vertically, then package footprint is reduced, but manufacturing complexity and alignment precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming through-silicon vias (TSVs) and interconnection structures in the substrate before mounting the semiconductor dies. This pre-fabrication of vertical interconnection pathways simplifies the subsequent die stacking process and reduces alignment requirements, as the connection points are already established in the lower dies.
Solution Approach 2:
The patent segments the packaging process into distinct stages: substrate preparation with TSVs, die mounting, wire bonding, and encapsulation. This segmentation allows each step to be optimized independently, reducing the cumulative complexity and precision requirements of the overall manufacturing process.
Data Source
AI summary
A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.