Low-Profile MEMS Package Stacking Without Thick Substrates
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Solution Overview
Problem
Current semiconductor device packaging technologies face challenges in reducing package height due to the thickness of substrates and interconnections, which limits the integration of stacked semiconductor dies and increases the package footprint.
Innovation Solution
The development of a low-profile MEMS package-on-package (PoP) device using a flip-chip semiconductor die stacked over a fan-out embedded wafer level ball grid array (Fo-eWLB) with modular interconnect units, which reduces the package height by optimizing electrical interconnection and using a standardized carrier for manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional substrate-based packaging is used, then structural support and electrical interconnection are provided, but package height increases and integration of stacked semiconductor dies is limited
Solution Approach 1:
The patent extracts and removes the traditional substrate from the packaging structure, replacing it with a carrier that provides only the necessary functions (structural support and electrical interconnection) without the bulk and height of a full substrate. This extraction of the substrate element directly reduces package height while maintaining essential functions.
Solution Approach 2:
The patent transitions from a traditional planar substrate-based architecture to a vertical stacked architecture where semiconductor dies are stacked in the Z-dimension. The carrier is positioned at the bottom of this vertical stack, enabling three-dimensional integration and reducing the horizontal footprint while managing height through vertical stacking rather than horizontal expansion.
2Length of moving object
If substrate thickness is reduced to lower package height, then manufacturing precision and structural integrity become more difficult to maintain
Solution Approach 1:
By extracting the substrate entirely and replacing it with a thinner carrier, the patent eliminates the need to control substrate thickness within tight tolerances. The carrier can be manufactured with greater thickness flexibility since it serves as a support structure rather than a functional interconnection medium, thereby reducing manufacturing precision requirements.
3Area of stationary object
If stacked semiconductor dies are integrated to reduce footprint, then package height increases due to substrate and interconnection thickness
Solution Approach 1:
The patent enables vertical stacking of semiconductor dies in the Z-dimension to achieve three-dimensional integration, which reduces the horizontal footprint. By replacing the thick substrate with a thin carrier, the height increase from stacking is minimized, allowing the device to benefit from reduced footprint without excessive height penalty.
Solution Approach 2:
The patent segments the packaging structure into distinct functional layers: a thin carrier at the bottom for support and interconnection, followed by stacked semiconductor dies, and finally a cap at the top. This segmentation allows each component to be optimized independently, with the carrier being thin to minimize height while the dies are stacked vertically to reduce footprint.
4Reliability
If complex interconnection structures are used to support stacked dies, then electrical performance improves but manufacturing cost increases
Solution Approach 1:
By extracting the substrate and replacing it with a simplified carrier, the patent reduces the complexity of the interconnection structure. The carrier provides essential electrical interconnection points without the complex multi-layer routing and via structures of a full substrate, thereby reducing manufacturing steps and cost while maintaining adequate electrical performance for the stacked die configuration.
Data Source
AI summary
A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system. The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.