MEMS Seal Ring Formation via Semiconductor Process Integration
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Solution Overview
Problem
Current methods for forming seal rings in micro electro mechanical systems (MEMS) are not compatible with standard semiconductor processes, making them costly for mass production and vulnerable to contamination and mechanical stress.
Innovation Solution
A method integrating conventional semiconductor processes to form seal rings by creating trenches and recesses in a substrate, filling them with oxide, and using contact hole etching and metal plug procedures to create a seal ring structure compatible with standard semiconductor processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard semiconductor processes are used to form seal rings, then manufacturing cost is reduced and compatibility is improved, but the seal ring structure becomes more complex requiring additional process steps
Solution Approach 1:
The patent combines seal ring formation with standard semiconductor manufacturing processes by integrating trench formation, oxide filling, and metal plug deposition into the existing process flow. The seal ring structure is formed using the same etching, deposition, and planarization steps already required for transistor fabrication, thereby reducing overall manufacturing cost while maintaining structural integrity
Solution Approach 2:
The seal ring is divided into distinct functional segments: a trench structure for mechanical anchoring, an oxide-filled region for stress management, and a metal plug for hermetic sealing. This segmentation allows each component to be optimized independently while using standard semiconductor process steps, balancing structural complexity with manufacturing simplicity
2Manufacturing precision
If conventional etching methods are used to form vias in silicon substrate, then via formation is achieved, but the process is not compatible with standard semiconductor manufacturing
Solution Approach 1:
The patent uses the same etching process steps already required for forming contact holes and trenches in standard CMOS fabrication to create the seal ring structure. The etch selectivity and depth control inherent in standard semiconductor processes automatically provide the necessary via formation precision without requiring additional specialized equipment or process steps
Solution Approach 2:
The standard semiconductor etching process is made multi-functional by using it for both device fabrication (trench formation for transistors) and seal ring structure creation. The same photoresist patterning, plasma etching, and etch stop layer techniques serve dual purposes, achieving precise via formation while maintaining full compatibility with existing manufacturing lines
3Reliability
If hermetically sealed cavity is created to protect MEMS, then protection from contamination is improved, but the device becomes more susceptible to mechanical stress
Solution Approach 1:
The patent applies different material properties to different regions of the seal ring structure: the oxide-filled trench provides a compliant, stress-absorbing medium, while the metal plug provides hermetic sealing. This local differentiation of material quality allows the structure to simultaneously resist contamination while managing mechanical stress through controlled deformation in the oxide region
Solution Approach 2:
The seal ring employs a composite structure combining silicon substrate, filled oxide material, and metal plug. The oxide layer acts as a stress buffer with lower modulus of elasticity, while the metal provides sealing integrity. This composite approach allows the hermetically sealed cavity to protect against contamination while the oxide layer absorbs and distributes mechanical stress, reducing its impact on the MEMS device
Data Source
AI summary
A method for forming a seal ring is disclosed. First, a substrate including a MEMS region, a logic region and a seal ring region is provided. Second, a trench is formed in the MEMS region and multiple recesses are formed in the seal ring region. An oxide fills the trench and the recesses. Later, a MOS is form in the logic region and a dielectric layer is formed on the substrate. Then, an etching procedure is carried out to partially remove the dielectric layer and simultaneously remove the oxide in the multiple recesses completely to form a seal ring space. Afterwards, a metal fills the seal ring space to from the seal ring.