MEMS-SOI Chip Electrical Packaging via Through-Hole Interconnects
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Solution Overview
Problem
Conventional electrical packaging methods for MEMS-SOI chips are unusable due to the small size of the units and the restriction of the fabrication process, which prevents the application of electric wiring on the surface, posing a challenge for connecting drive electrodes to PCBs without damaging the movable structures.
Innovation Solution
A method involving a sequence of isolating and conducting layers with conductive through holes and independent electrodes, allowing for one-to-one electrical connection between conductive structures and electrodes, while protecting the MEMS movable structures with an isolating apparatus, enabling compatibility with standard packaging processes and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect the chip to the lead frame, then electrical connection is achieved, but the hermetic seal is compromised and reliability decreases
Solution Approach 1:
The patent merges the electrical connection function and hermetic sealing function into a single integrated structure. The lead frame itself is designed to provide both electrical connectivity and hermetic sealing, eliminating the need for separate wire bonding while maintaining both functions. This is achieved through direct metallurgical bonding of the lead frame to the chip, creating a unified encapsulation system that preserves hermetic integrity.
Solution Approach 2:
The patent extracts the wire bonding step from the manufacturing process by implementing direct lead frame-to-chip bonding. This removes the intermediate wire bonding component that was compromising the hermetic seal, while still achieving the necessary electrical connection through the lead frame structure itself.
2Manufacturing precision
If conventional encapsulation processes are used, then manufacturing is simplified, but manufacturing precision and hermetic seal quality deteriorate
Solution Approach 1:
The patent applies preliminary action by pre-forming the lead frame with integrated bonding structures and alignment features before the encapsulation process. The lead frame is prepared in advance with specific geometries that enable precise positioning and hermetic bonding to the chip, ensuring high sealing precision without requiring complex real-time adjustments during encapsulation.
3Reliability
If multiple processing steps are used to achieve hermetic seal, then seal quality improves, but manufacturing time and complexity increase
Solution Approach 1:
The patent combines multiple processing steps into a single integrated encapsulation process. The lead frame bonding, hermetic sealing, and electrical connection are performed simultaneously in one manufacturing step, rather than as separate sequential operations. This integration maintains high seal quality while significantly reducing the total manufacturing cycle time.
Data Source
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AI summary
This application provides a MEMS chip and an electrical packaging method for a MEMS chip. The MEMS chip includes a MEMS device layer, a first isolating layer located under the MEMS device layer, and a first conducting layer located under the first isolating layer. At the first isolating layer, there are corresponding quantities of first conductive through holes in locations corresponding to conductive structures in a first region and in locations corresponding to electrodes in a second region. At the first conducting layer, there are M electrodes independent of each other, and the M electrodes are respectively connected to M first conductive through holes, where M is set based on a quantity of the conductive structures and a quantity of the electrodes in the second region. At the first conducting layer, electrodes in locations corresponding to the conductive structures in the first region are electrically connected in a one-to-one correspondence to electrodes in locations corresponding to the electrodes in the second region. In this way, electrical packaging of a MEMS-SOI chip is implemented.