Batch Fabricated MEMS Test Probes for Fine Pitch Interconnects
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Solution Overview
Problem
The challenge lies in manufacturing high-density and fine-pitch interconnect structures for electrical test apparatuses, where existing technologies face issues with increased time, cost, and decreased accuracy due to the serial assembly of test probes, which becomes prohibitive as the number of interconnects grows and semiconductor bump or pad pitch decreases.
Innovation Solution
The implementation of three-dimensional batch fabrication processes to form multiple test probes simultaneously on a substrate, using lithography-based methods that reduce manufacturing time and probe-to-probe variations, allowing for the production of hundreds or thousands of probes in the same time as a single probe, thereby breaking the cost and time scaling curve.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If serial one-interconnect-at-a-time assembly approach is used, then manufacturing process is simple, but manufacturing time and cost increase significantly while accuracy decreases as number of interconnects increases
Solution Approach 1:
The patent merges multiple interconnect assembly operations into a single batch fabrication process. Multiple test probes are assembled simultaneously on a substrate in parallel, rather than sequentially one at a time. This combining of operations dramatically reduces manufacturing time and breaks the linear scaling curve of cost and time with respect to the number of interconnects.
Solution Approach 2:
The patent transitions from one-dimensional sequential assembly to two-dimensional parallel batch fabrication. By arranging multiple interconnects in a spatial array on the substrate and fabricating them simultaneously across the substrate area, the process exploits the spatial dimension to achieve parallelism and improve productivity.
2Ease of manufacture
If serial one-interconnect-at-a-time assembly approach is used, then manufacturing process is simple, but manufacturing cost increases with number of interconnects
Solution Approach 1:
The patent merges multiple interconnect assembly operations into a single batch fabrication process. Multiple test probes are assembled simultaneously on a substrate in parallel, rather than sequentially one at a time. This combining of operations dramatically reduces manufacturing time and breaks the linear scaling curve of cost and time with respect to the number of interconnects.
3Ease of manufacture
If serial one-interconnect-at-a-time assembly approach is used, then manufacturing process is simple, but accuracy and consistency decrease as number of interconnects increases
Solution Approach 1:
The patent merges multiple interconnect assembly operations into a single batch fabrication process. Multiple test probes are assembled simultaneously on a substrate in parallel, rather than sequentially one at a time. This combining of operations dramatically reduces manufacturing time and breaks the linear scaling curve of cost and time with respect to the number of interconnects.
Solution Approach 2:
The patent achieves homogeneity in interconnect properties by fabricating all probes in a batch under identical process conditions simultaneously. This uniform treatment eliminates variations that accumulate in sequential processes, resulting in consistent probe-to-probe characteristics and improved manufacturing precision.
4Adaptability or versatility
If number of interconnects increases and pitch decreases, then testing capability improves, but existing manufacturing technology becomes prohibitive
Solution Approach 1:
The patent transitions from one-dimensional sequential assembly to two-dimensional parallel batch fabrication. By arranging multiple interconnects in a spatial array on the substrate and fabricating them simultaneously across the substrate area, the process exploits the spatial dimension to achieve parallelism and improve productivity.
Solution Approach 2:
The patent merges multiple interconnect assembly operations into a single batch fabrication process. Multiple test probes are assembled simultaneously on a substrate in parallel, rather than sequentially one at a time. This combining of operations dramatically reduces manufacturing time and breaks the linear scaling curve of cost and time with respect to the number of interconnects.
Data Source
AI summary
An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.