MEMS Thermal Oxide Isolation Layer for Parasitic Capacitance Reduction
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Solution Overview
Problem
MEMS devices with thin thermal silicon dioxide isolation layers suffer from parasitic capacitive coupling loss and performance degradation due to poor uniformity and surface roughness issues with thicker TEOS oxide deposition layers, leading to lower signal-to-noise ratio and etching problems.
Innovation Solution
A MEMS device structure featuring a substrate with a device stopper and a thick thermal dielectric isolation layer formed by thermal oxidation, which surrounds a device cavity and reduces parasitic capacitive coupling loss while maintaining low surface roughness, thereby improving signal uniformity and preventing undercut during the release process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thin thermal silicon oxide isolation layer (up to 2 um) is used, then the device structure is simpler and manufacturing is easier, but parasitic capacitive coupling loss increases leading to lower signal-to-noise ratio
Solution Approach 1:
The patent changes the thickness parameter of the isolation layer from thin (2 um) to thick (5-20 um), which fundamentally alters the electrical isolation performance and reduces parasitic capacitance, thereby improving signal-to-noise ratio while maintaining manufacturing feasibility through standard thermal oxidation processes
2Reliability
If a thick TEOS oxide isolation layer is deposited to reduce parasitic capacitance, then the isolation effectiveness improves, but surface roughness increases causing poor AlN stress uniformity and device performance degradation
Solution Approach 1:
The patent replaces the mechanical deposition process (TEOS CVD) with a thermal oxidation process, which produces a denser, smoother oxide layer with superior surface finish while achieving the same or better isolation effectiveness, thereby eliminating the surface roughness problem that causes AlN stress non-uniformity
3Length of stationary object
If a deposited TEOS oxide isolation layer is used, then thicker isolation is achieved, but undercut occurs during VHF etching and etch uniformity across the wafer deteriorates
Solution Approach 1:
The patent changes the material composition parameter of the isolation layer from deposited TEOS oxide to thermally grown silicon oxide, which has fundamentally different etch characteristics in VHF, eliminating the undercut phenomenon and achieving superior etch uniformity across the entire wafer surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces parasitic capacitive coupling loss and maintains improved uniformity and stress distribution across the active device layer, enhancing the performance and reliability of MEMS devices like microphones and sensors by restricting undercut and maintaining low surface roughness.
Implementation Method 1
A thermal dielectric isolation layer may be arranged over the device stopper and the substrate
Data Source
AI summary
A method of forming a MEMS device includes providing a substrate having a device stopper. The device stopper is integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may be formed in the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be formed over the thermal dielectric isolation layer and the device cavity.