MEMS Through-Hole Structure to Prevent Metal Layer Peeling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing MEMS devices face issues with peeling of metal layers from through-holes, which disrupt the controlled paths for charged particles, leading to poor control and efficiency.

Innovation Solution

The MEMS device design includes through-holes with lower portions wider than upper portions, ensuring that the metal layer does not extend to the sidewalls of the lower portions, thereby improving adhesion and reducing peeling, and using a conductive adhesion layer to enhance the bonding of the metal layer with underlying layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If the metal layer extends to the sidewalls of the lower portions of through-holes, then the coverage and continuity of the metal layer is improved, but the adhesion of the metal layer deteriorates causing peeling

Engineering Contradiction:
Improvemetal layer continuityVSAvoidmetal layer adhesion
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent applies local quality by creating a wider lower portion in the through-holes where the metal layer is deposited. This local geometric modification ensures that the metal layer does not extend to the sidewalls in the lower portions, preventing peeling while maintaining continuity in the upper portions where full coverage is achieved.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If the through-holes have uniform width, then the manufacturing process is simplified, but the metal layer adhesion deteriorates causing peeling from deep portions

Engineering Contradiction:
Improvethrough-hole fabricationVSAvoidmetal layer adhesion
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The through-holes are designed with non-uniform width, featuring wider lower portions and narrower upper portions. This local geometric variation is achieved through a two-step etching process that first creates initial through-holes and then selectively widens the lower portions, resolving the adhesion problem while maintaining manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs preliminary action by first forming the through-holes with a standard etching process, then performing a second etching step to widen the lower portions before metal layer deposition. This preliminary geometric preparation ensures optimal metal layer adhesion from the beginning of the metallization process.

Inventive Principle:
Principle #10Preliminary action

3Stability of the object's composition

If the metal layer is deposited conformally in deep through-holes, then the coverage is improved, but the metal layer peels from the deep portions disrupting charged particle paths

Engineering Contradiction:
Improvemetal layer coverageVSAvoidpeeling disrupting charged particle paths
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by modifying the through-hole geometry at the lower portions to be wider, which prevents the metal layer from extending to the sidewalls in these regions. This local geometric adjustment eliminates peeling while maintaining continuous metal layer coverage in the upper portions, ensuring uninterrupted charged particle paths.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250353735A1MEMS structure with reduced peeling and methods forming the same
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250353735A1 patent drawing
  • US20250353735A1 patent drawing
  • US20250353735A1 patent drawing

AI summary

A method includes forming an interconnect structure over a semiconductor substrate. The interconnect structure includes a plurality of dielectric layers, and the interconnect structure and the semiconductor substrate are in a wafer. A plurality of metal pads are formed over the interconnect structure. A plurality of through-holes are formed to penetrate through the wafer. The plurality of through-holes include top portions penetrating through the interconnect structure, and middle portions underlying and joining to the top portions. The middle portions are wider than respective ones of the top portions. A metal layer is formed to electrically connect to the plurality of metal pads. The metal layer extends into the top portions of the plurality of through-holes.