MEMS Packaging via TSV and Segmentation to Reduce CTE Mismatch Stress
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Solution Overview
Problem
Current MEMS packaging technologies face challenges in reducing packaging stresses caused by coefficient of thermal expansion mismatches between materials, leading to performance issues and increased costs due to complex assembly processes and high component counts.
Innovation Solution
The implementation of a novel package structure using through-silicon via (TSV) technology allows direct stacking of MEMS devices on ASICs, which are then mounted to PCBs, minimizing footprint and eliminating the need for wire bonding, along with stress relief structures that separate critical components from packaging stresses using flexible regions and hermetic seals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MEMS and ASIC are packaged near one another to reduce footprint and improve performance, then device integration and performance are improved, but packaging stress increases due to CTE mismatch between organic substrate and silicon device
Solution Approach 1:
The patent divides the package into separate stress zones by positioning the MEMS device and ASIC in close proximity but isolating their stress fields. The MEMS device is packaged in a first package with its own stress relief structures, while the ASIC is packaged separately in a second package, allowing both components to be integrated near each other without their thermal expansion stresses compounding together.
Solution Approach 2:
The patent introduces compliant interconnect structures and stress relief features as intermediaries between the MEMS device and ASIC. These intermediary elements absorb and isolate the thermal expansion mismatch stresses, allowing the MEMS and ASIC to be positioned near each other for improved performance while preventing stress transmission between the two components.
2Reliability
If hermetic seal is implemented to prevent water ingress and maintain performance, then device reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the hermetic sealing function with the existing package structure by integrating the seal around the MEMS device cavity within the first package. Rather than adding a separate hermetic sealing system, the seal is merged into the package design, providing moisture protection while maintaining a relatively simple manufacturing process.
Solution Approach 2:
The package structure is designed to provide self-sealing capabilities through the arrangement of the MEMS device within the first package. The seal is configured to automatically maintain hermeticity through the package structure itself, reducing the need for additional active sealing mechanisms or complex assembly steps.
3Strength
If CTE mismatch between FR-4 substrate and silicon device is addressed using stiff solder, then mechanical strength is improved, but thermal stress increases during temperature changes
Solution Approach 1:
The patent employs compliant interconnect structures and flexible bonding interfaces between the MEMS device and ASIC, as well as between the ASIC and substrate. These flexible connections replace traditional stiff solder joints, allowing the structure to accommodate thermal expansion differences between FR-4 and silicon without generating excessive thermal stress, while still maintaining adequate mechanical strength.
Solution Approach 2:
The patent changes the mechanical parameters of the interconnect structures by using compliant materials and designs with different stiffness characteristics. Instead of using stiff solder that transmits thermal stress, the patent employs interconnects with optimized compliance parameters that can absorb thermal expansion mismatch, reducing thermal stress while maintaining joint integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces packaging stresses, improves performance, and lowers costs by enabling faster assembly and more efficient wafer-level processing, while providing a reliable hermetic seal that minimizes environmental interference and stress impacts on MEMS devices.
Implementation Method 1
The implementation of a novel package structure using through-silicon via (TSV) technology allows direct stacking of MEMS devices on ASICs, which are then mounted to PCBs, minimizing footprint and eliminating the need for wire bonding
Implementation Method 2
A major source of package stress on MEMS devices is a mismatch of the coefficient of thermal expansion ('CTE') between device materials. This is commonly seen in the CTE mismatch between an organic substrate material such as FR-4 and a silicon device.
Implementation Method 3
stress relief structures that separate critical components from packaging stresses using flexible regions and hermetic seals
Implementation Method 4
A critical feature of many MEMS devices is a hermetic seal that prevents the flow of water into the device. If water or water vapor seeps into a MEMS package, capacitances that affect performance of the MEMS can vary uncontrollably, negatively impacting function.
Data Source
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AI summary
One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit.