MEMS Via Interlock Geometry for Thermal Stress Reduction
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Solution Overview
Problem
Existing via and bus geometries in MEMS devices face challenges with thermal expansion, electrical resistance, and inductance, particularly when multiple microswitches are connected in parallel, requiring improved geometries for efficient heat dissipation and minimal resistance.
Innovation Solution
The proposed solution involves a substrate with vias that are at least partly filled with an electrically conductive material, featuring a trench geometry with interlocks to constrain thermal expansion and a prismatic trapezoidal shape aligned with the bus, allowing for reduced thermally-induced stress and increased current capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are placed in close proximity to MEMS structures to maximize thermal dissipation and minimize resistance, then electrical performance improves, but thin film stress induced by thermal expansion of the via material worsens
Solution Approach 1:
The via structure is designed with non-uniform geometry, being larger at the bottom and smaller at the top, creating different structural properties at different locations. This local variation in via dimensions allows the bottom portion to provide strong thermal and electrical conduction paths while the reduced top portion minimizes stress on the thin films near the MEMS structures.
Solution Approach 2:
The via geometry transitions from a simple vertical cylinder to a three-dimensional tapered structure with varying cross-sectional area along its length. This dimensional change enables the via to simultaneously achieve low resistance (through adequate volume of conductive material) and low stress (through reduced footprint at the surface level where thin films are located).
2Power
If multiple microswitches are connected in parallel to provide higher current capacity, then current handling ability improves, but device complexity worsens
Solution Approach 1:
Multiple via structures are merged into a shared common via that serves multiple microswitches in parallel. This consolidation reduces the total number of individual via connections needed, simplifying the overall device structure while maintaining the high current capacity achieved through parallel microswitch operation.
Solution Approach 2:
The common via structure is designed to serve multiple functions simultaneously: it provides electrical connection for multiple parallel microswitches, acts as a thermal dissipation path for multiple devices, and serves as a mechanical anchor point. This multi-functionality reduces device complexity by eliminating redundant structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces thermal expansion, minimizes electrical resistance, and enhances current carrying capacity while maintaining compact dimensions, suitable for high-power MEMS switch applications.
Implementation Method 1
The via is at least partly filled with an electrically conductive material. Vias generally have good electrical conductivity and heat transfer.
Implementation Method 2
MEMS devices need optimal heat dissipation and minimal electrical resistance to avoid destructive heat accumulation. Vias generally have good electrical conductivity and heat transfer.
Implementation Method 3
The via is configured to define an interlock positioned to reduce thermally-induced expansion of the electrically conductive material with respect to the first surface.
Data Source
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AI summary
An electrical through-connection, or via, that passes through a substrate (22) to a bus (28) on a first surface (21) of the substrate (22). The via may be configured with an interlock (46) such that the electrically conductive core (60) of the via is constrained to thermally expand towards the second surface (23), away from the bus (28), thus preventing damage to the bus (28). The interlock (46) may be a local constriction or enlargement of the via near the first surface (21) of the substrate (22). The via may be greater in length along the bus (28) than a unit spacing of beams (30) in a parallel microswitch array (20) actuated in unison along the bus (28). The via may be narrower in width than in length, and may form a trapezoidal geometry that is larger at the second surface (23) of the substrate (22) than at the first surface (21).