MEOL Strap Layout for Standard Cells With Lower Parasitic Capacitance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor fabrication processes for integrated circuits face challenges in optimizing current flow and reducing parasitic capacitance during the middle-end-of-line (MEOL) process, which affects the operation speed and performance of semiconductor structures.

Innovation Solution

The implementation of conductive metal segments and local conductive segments with specific geometries and alignments, along with the omission of certain conductive vias, to create additional current paths and reduce parasitic capacitance, thereby enhancing current flow and operational speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional conductive structures are used in MEOL process, then manufacturing simplicity is maintained, but current flow is insufficient and parasitic capacitance increases

Engineering Contradiction:
Improvecurrent flowVSAvoidconductive structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive structure is divided into multiple segments including first conductive segments, second conductive segments, third conductive segments, and local conductive segments. Each segment serves a specific function in creating additional current paths and reducing parasitic capacitance, thereby improving current flow without requiring a complete structural overhaul

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the conductive structure are assigned different properties and functions. For example, local conductive segments are strategically placed in specific regions to reduce parasitic capacitance between gates, while other segments are optimized for current conduction. This localized optimization allows improvement in specific areas without uniformly increasing complexity throughout the entire structure

Inventive Principle:
Principle #3Local quality

2Speed

If additional current paths are created through conductive segments, then operation speed improves, but manufacturing complexity increases

Engineering Contradiction:
Improveoperation speedVSAvoidmanufacturing ease
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The conductive segments are pre-configured in the semiconductor structure during fabrication to establish multiple current paths before the device operates. The first, second, and third conductive segments are formed in advance with specific geometries and positions that will automatically create the desired current paths when the device is activated, eliminating the need for post-fabrication modifications

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Multiple conductive segments are merged into a unified structure where the first, second, third conductive segments and local conductive segments work together as an integrated system. This merging allows the structure to achieve multiple functions (current conduction, parasitic capacitance reduction) simultaneously through a single integrated design rather than separate components

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12261113B2Middle-end-of-line strap for standard cell
Publication Date: 2025.03.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12261113B2 patent drawing
  • US12261113B2 patent drawing
  • US12261113B2 patent drawing

AI summary

A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.