MEPV Wafer Interconnect via Planar Spring Dielectric
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Solution Overview
Problem
The fabrication of microsystem enabled photovoltaic (MEPV) cells and integrated sensors requires efficient methods for forming connections between devices on a wafer, involving multiple processing steps for separation, alignment, and conductor fabrication, which can be complex and inefficient.
Innovation Solution
A method involving a substrate with device cells, a first dielectric layer, and metal interconnects across cell boundaries, followed by a second dielectric layer with patterned openings or tethers for mechanical flexibility, allowing for the formation of interconnected device cells with enhanced assembly and singulation capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple processing steps are used for separation, alignment, and conductor fabrication, then connections between devices can be formed, but the fabrication process becomes complex and inefficient
Solution Approach 1:
The patent combines separation, alignment, and conductor fabrication into a single integrated process. Conductors are deposited across cell boundaries while cells are still attached to the wafer, eliminating the need for separate alignment and conductor fabrication steps that would otherwise require multiple processing cycles and precise manual or automated alignment procedures.
Solution Approach 2:
The patent performs conductor deposition before cell separation. By depositing the conductor material across the boundary between cells while they remain on the wafer, the alignment and positioning are predetermined by the wafer geometry, eliminating the need for post-separation alignment operations and simplifying the overall fabrication sequence.
2Reliability
If cells are separated and aligned individually, then connections between cells can be established, but the process time and complexity increase
Solution Approach 1:
The patent performs conductor deposition before cell separation. By depositing the conductor material across the boundary between cells while they remain on the wafer, the alignment and positioning are predetermined by the wafer geometry, eliminating the need for post-separation alignment operations and simplifying the overall fabrication sequence.
Solution Approach 2:
The patent combines separation, alignment, and conductor fabrication into a single integrated process. Conductors are deposited across cell boundaries while cells are still attached to the wafer, eliminating the need for separate alignment and conductor fabrication steps that would otherwise require multiple processing cycles and precise manual or automated alignment procedures.
3Stability of the object's composition
If rigid dielectric layers are used for interconnect protection, then electrical connections are stable, but mechanical flexibility of the assembly is reduced
Solution Approach 1:
The patent employs a flexible dielectric layer that can be deposited conformally over the conductor and cell assembly. This flexible layer maintains electrical insulation and protects the conductor while allowing the overall structure to bend or conform to different geometries, thus providing both electrical stability and mechanical adaptability.
Solution Approach 2:
The patent uses a composite structure combining rigid and flexible components. The dielectric layer may be composed of materials or structured in a way that provides both mechanical flexibility and electrical stability, allowing the assembly to maintain functional integrity while adapting to mechanical deformations or different mounting configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the formation of interconnected device cells by providing mechanical flexibility and efficient singulation, reducing the complexity of the fabrication process while maintaining electrical connections between cells.
Implementation Method 1
depositing a metal interconnect on the first dielectric layer such that the deposited interconnect is electrically connected to at least two of the device cells
Implementation Method 2
depositing a first dielectric layer on the device layer; and depositing a second dielectric layer over the first dielectric layer and over the interconnect
Data Source
AI summary
A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.