Merging Equivalent Logic Blocks in Circuit Design
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Solution Overview
Problem
Replication of logic blocks in circuit designs, particularly in programmable integrated circuits like FPGAs, leads to increased circuit area occupation and power consumption due to unnecessary blocks, and creates fitting problems due to control set requirements.
Innovation Solution
A method to merge replicate logic blocks with equivalent logic into a single replacement block, based on factors like timing criticality, congestion, and power consumption, after the circuit design has been placed, to optimize performance and reduce unnecessary blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logic blocks are replicated to reduce fanout and create fanout-free regions, then combinatorial synthesis optimizations are improved, but circuit area occupation increases and power consumption increases
Solution Approach 1:
The patent merges replicate logic blocks that have equivalent logic functions into a single logic block. This is achieved by analyzing the circuit design to identify replicate blocks, determining whether they can be merged based on equivalence checking, and then consolidating them into one block that performs the same function, thereby reducing circuit area while maintaining synthesis optimization benefits
Solution Approach 2:
The patent identifies and removes unnecessary replicate logic blocks from the circuit design after placement. By discarding redundant blocks that are no longer needed post-placement, the circuit area is recovered and reduced, while the essential logic functions are preserved through the remaining necessary blocks
2Ease of operation
If logic blocks are replicated to reduce fanout, then fanout on output side is reduced, but number of pins on input side increases
Solution Approach 1:
The patent merges replicate logic blocks that have equivalent logic functions into a single logic block. This consolidation reduces the number of input pins required, as the merged block receives inputs once and distributes them to multiple outputs, rather than requiring separate input pins for each replicate block
3Adaptability or versatility
If replicate logic blocks are used in FPGA designs, then logic functionality is achieved, but fitting problems occur due to control set requirements
Solution Approach 1:
The patent merges replicate logic blocks into a single block that can be properly fitted to FPGA control sets. By consolidating replicates, the design reduces the number of flip-flops that need to be driven by control signals, making it easier to satisfy FPGA control set requirements and avoid fitting problems while maintaining the necessary logic functionality
4Area of stationary object
If unnecessary replicate logic blocks are removed, then circuit area is reduced, but timing accuracy may be affected
Solution Approach 1:
The patent performs equivalence checking and merge determination during the placement stage, before final timing closure. By preliminarily identifying which replicate blocks can be merged based on logical equivalence, the design ensures that timing-critical replicates are preserved while non-critical ones are merged, maintaining timing accuracy while reducing area
Solution Approach 2:
The patent uses timing analysis feedback to determine whether replicate logic blocks should be merged or preserved. By analyzing timing paths and identifying which replicates are on critical paths, the design preserves timing accuracy by keeping necessary replicates while merging others, using timing feedback to guide the merge decision
Data Source
AI summary
Approaches for merging replicate logic blocks of a circuit design. Groups of replicate logic blocks in a placed circuit design are determined. For the replicate logic blocks in each group, a determination is made whether or not to merge replicate logic blocks in a subset of the replicate logic blocks into a respective single replacement logic block for the subset. In response to determining to merge the replicate logic blocks in the subset, the replicate logic blocks in the subset are replaced in the circuit design with the respective replacement logic block. The circuit design having the replacement logic block is stored in a memory by a processor executing the process.