Merge Execution Unit for Microinstruction Permutation
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Solution Overview
Problem
In microprocessors, merge and permutation instructions consume significant processing time and power due to the need to regenerate each byte of the result in every instruction execution, even if only some data bytes have changed, as partially writing a register is impossible in out-of-order machines.
Innovation Solution
A high-efficiency merge execution circuit using a bank of multiplexers (MUXs) that selectively outputs data elements to a destination register based on merge control words, allowing simultaneous generation of multiple data elements in a merge result, reducing the number of micro-operations required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each byte of the result is generated in each instruction execution, then the merge and permutation result is complete and accurate, but processing time and power consumption increase significantly
Solution Approach 1:
The patent segments the merge and permutation operation into individual byte-level micro-operations. Each byte position is handled independently through separate micro-instructions, allowing the processor to execute only the necessary bytes rather than regenerating all bytes. This segmentation enables selective execution while maintaining result accuracy.
Solution Approach 2:
The patent implements partial action by allowing execution of only the necessary portion of the merge operation. When combined with the merge hint mechanism, the processor can determine which bytes have changed and execute micro-operations only for those bytes, avoiding excessive generation of unchanged data and reducing overall execution time.
2Reliability
If each byte of the result is generated in each instruction execution, then the merge result is complete, but power consumption increases significantly
Solution Approach 1:
The patent segments the power-consuming merge operation into discrete byte-level micro-operations. By controlling execution at the byte level through the micro-code interpreter, the system consumes power only for the necessary bytes rather than all bytes, reducing overall power consumption while maintaining result completeness.
Solution Approach 2:
The patent applies partial action by executing only the necessary micro-operations for changed bytes. The merge hint mechanism enables the processor to identify which bytes require processing and execute only those partial operations, avoiding excessive power consumption from regenerating unchanged data.
3Speed
If a bank of multiplexers is used to simultaneously generate multiple data elements, then processing speed increases, but device complexity increases
Solution Approach 1:
The patent employs dynamic control of the merge unit through a micro-code interpreter that dynamically selects and sequences micro-operations based on the specific merge requirements. This dynamic approach allows the use of a bank of multiplexers for parallel processing while managing complexity through software-controlled operation sequences rather than hardwired logic for all possible operations.
Solution Approach 2:
The patent introduces a micro-code interpreter as an intermediary between the instruction set and the merge unit hardware. This intermediary translates high-level merge instructions into sequences of simple micro-operations that control the multiplexer bank, enabling complex merge functionality while keeping the hardware structure manageable through layered control.
Data Source
AI summary
A merge unit configured to perform merge and permutation micro-operations by multiplexing data bytes of the inputs to simultaneously produce multiple data bytes of a merge and permutation result. Particularly, the merge unit includes a bank of MUXs arranged in parallel, each corresponding to one or more different data bytes in the merge result. When the merge unit is provided with a set of inputs, each MUX multiplexes the data bytes of the set of inputs (e.g., all the data bytes of the set of inputs) to selectively output a data byte to a particular location of the destination register storing the merge result. The selection by each MUX is individually controlled by a set of merge control words which identify a data byte location in an input and identify an input from the set of inputs.