Merging Memory Ordering Tracking for Load Operations

Solution Overview

Problem

Data processing systems face performance constraints due to memory ordering requirements, which can lead to stalls in load operations, and existing solutions that track these requirements consume significant power and circuit area, especially as the number of operations increases.

Innovation Solution

The implementation of load issuing circuitry and memory ordering tracking storage circuitry that allows for the issuance of load operations out-of-order, with control circuitry to determine if re-issuing is necessary based on tracking information, and merging memory ordering tracking information for multiple load operations into a single entry to reduce circuit area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory ordering tracking information is stored for each issued load operation, then architectural correctness is maintained, but circuit area and power consumption increase significantly

Engineering Contradiction:

Improvearchitectural correctnessVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges memory ordering tracking information for multiple load operations into a single shared entry in the tracking storage circuitry. Instead of allocating separate tracking entries for each load operation, the system consolidates tracking data for multiple operations, thereby reducing the total number of tracking entries required and decreasing circuit area while maintaining the ability to detect ordering violations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent makes a single tracking storage entry serve multiple load operations simultaneously. The tracking entry is designed to track ordering information for multiple load operations universally, allowing the same hardware structure to handle different load operations without requiring dedicated tracking resources for each operation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If memory ordering tracking information is stored for each issued load operation, then architectural correctness is maintained, but power consumption increases significantly

Engineering Contradiction:

Improvearchitectural correctnessVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent merges memory ordering tracking information for multiple load operations into a single shared entry in the tracking storage circuitry. Instead of allocating separate tracking entries for each load operation, the system consolidates tracking data for multiple operations, thereby reducing the total number of tracking entries required and decreasing circuit area while maintaining the ability to detect ordering violations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent makes a single tracking storage entry serve multiple load operations simultaneously. The tracking entry is designed to track ordering information for multiple load operations universally, allowing the same hardware structure to handle different load operations without requiring dedicated tracking resources for each operation.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If load operations are issued in-order to satisfy memory ordering requirements, then memory ordering correctness is maintained, but processing performance decreases due to stalls

Engineering Contradiction:

Improvememory ordering correctnessVSAvoidprocessing performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic load issuance where the system can adaptively issue load operations out-of-order when tracking information indicates no ordering violation would occur. The load issuing circuitry dynamically adjusts the issuance order based on real-time tracking information from the storage circuitry, allowing performance optimization while maintaining correctness when possible.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent uses feedback from the memory ordering tracking storage circuitry to control load issuance. The tracking information provides feedback about whether out-of-order issuance would violate memory ordering requirements, allowing the load issuing circuitry to make informed decisions about issuance order and enabling out-of-order execution when safe.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11194574B2Merging memory ordering tracking information for issued load instructions

Publication Date: 2021.12.07 ARM LTD

AI summary

An apparatus is described, comprising load issuing circuitry configured to issue load operations to load data from memory, and memory ordering tracking storage circuitry configured to store memory ordering tracking information on issued load operations. The apparatus also includes control circuitry configured to access the memory ordering tracking storage circuitry to determine, using the memory ordering tracking information, whether at least one load operation has been issued in disagreement with a memory ordering requirement, and, if so, to determine whether to re-issue one or more issued load operations or to continue issuing load operations despite disagreement with the memory ordering requirement. Furthermore, the control circuitry is capable of merging the memory ordering tracking information for a plurality of issued load operations into a merged entry in the memory ordering tracking storage circuitry.