Merging Partial Reconfiguration Bitstreams for IC Design

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Circuit designers face the challenge of managing a high number of partial configuration bitstream files for multiple reconfiguration regions in programmable IC devices, requiring individual updates which can be time-consuming and inefficient.

Innovation Solution

A method to merge two or more partial reconfiguration bitstream files into a single merged file, allowing concurrent configuration of multiple regions on an integrated circuit device using a computer-aided design tool, thereby reducing the number of files and streamlining the reconfiguration process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple partial configuration bitstream files are generated for each partial reconfiguration region, then each region can be configured individually, but the number of files to manage increases significantly

Engineering Contradiction:
Improveindividual region configuration capabilityVSAvoidnumber of configuration files
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple partial configuration bitstream files into a single unified configuration file that contains configuration data for multiple partial reconfiguration regions. This unified file structure allows the system to maintain the ability to configure individual regions while eliminating the need to manage multiple separate files, directly resolving the contradiction between individual region configuration capability and file management complexity

Inventive Principle:
Principle #5Merging (Combining)

2Manufacturing precision

If individual partial configuration bitstream files are used for each region, then precise control over each region is achieved, but the time required to update multiple regions increases

Engineering Contradiction:
Improveregion configuration precisionVSAvoidreconfiguration time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary organization of configuration data by pre-structuring the unified configuration file to contain all necessary region configurations in a single file. This preliminary organization allows the system to load and configure multiple regions simultaneously or in sequence from one file, rather than sequentially processing multiple separate files, thus reducing reconfiguration time while maintaining precise control over each region

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If multiple partial configuration bitstream files are generated, then each region can be updated independently, but the administrative burden of tracking and managing files increases

Engineering Contradiction:
Improveindependent region update capabilityVSAvoidfile management ease
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The patent combines multiple region configuration data into a single unified configuration file with a structured format that identifies and separates configurations for different partial reconfiguration regions. This merging approach maintains independent update capability by allowing selective application of specific region configurations from the unified file, while dramatically improving file management ease by reducing the number of files from multiple to one

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8997033B1Techniques for generating a single configuration file for multiple partial reconfiguration regions
Publication Date: 2015.03.31 ALTERA CORP
  • US8997033B1 patent drawing
  • US8997033B1 patent drawing
  • US8997033B1 patent drawing

AI summary

Techniques for compiling an integrated circuit (IC) design with a computer-aided design tool are provided. The IC design may include multiple dynamic configuration regions that may be updated during runtime without affecting other regions on the IC device. When an IC design is compiled for an IC device, dynamic configuration regions in the IC design are identified. The computer-aided design tool may generate a partial configuration file for each identified dynamic configuration region. Two or more partial reconfiguration files may be combined to obtain a single partial configuration file that may then be used to configure respective dynamic configuration regions on the IC device.