Merge Sort Accelerator for Non-Linear Data Processing
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Solution Overview
Problem
Current hardware accelerators, such as matrix multiplication accelerators, are ineffective in performing non-linear mathematical operations like merge sort, min, max, sort, median, rank, pool, and find efficiently.
Innovation Solution
A merge sort accelerator is introduced, comprising a pre-processing stage, a merge sort network with multiple sorting stages, an accumulator stage, and a post-processing stage, which processes input vectors by expanding analysis groups to a power of 2, sorting elements, and selecting specific elements for output, enabling efficient execution of these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If general-purpose host processor executes merge sort operations, then device complexity is low, but productivity is insufficient
Solution Approach 1:
The merge sort accelerator is divided into distinct functional modules: pre-processing stage, merge sort network with multiple sorting stages, accumulator stage, and post-processing stage. Each stage handles specific operations, allowing parallel processing and improving overall productivity while managing complexity through modular design.
Solution Approach 2:
The merge sort accelerator is designed to perform multiple operations including merge sort, min, max, sort, median, rank, pool, and find operations. The same hardware infrastructure supports various sorting algorithms and data analysis functions, achieving high productivity across diverse operations without proportionally increasing device complexity.
2Manufacturing precision
If matrix multiplication accelerator is used for non-linear operations, then device complexity is low, but manufacturing precision is insufficient
Solution Approach 1:
Different stages of the accelerator are optimized for specific operation types. The pre-processing stage handles data preparation, the merge sort network performs sorting with configurable comparison operations, the accumulator stage manages reduction operations, and the post-processing stage handles output formatting. This localized optimization ensures high manufacturing precision for each operation type while managing overall design complexity.
Solution Approach 2:
The accelerator incorporates configurable sorting stages that can be selectively enabled or disabled based on the specific operation being performed. The network adapts its structure and behavior dynamically to match the required operation, achieving high precision for various non-linear operations without requiring a completely different hardware design for each operation.
Data Source
AI summary
A merge sort accelerator (MSA) includes a pre-processing stage configured to receive an input vector and generate a pre-processing output vector based on a pre-processing instruction and the input vector. The MSA also includes a merge sort network having multiple sorting stages configured to be selectively enabled. The merge sort network is configured to receive the pre-processing output vector and generate a sorted output vector based on a sorting instruction and the pre-processing output vector. The MSA includes an accumulator stage configured to receive the sorted output vector and update an accumulator vector based on the accumulator instruction and the sorted output vector. The MSA also includes a post-processing stage configured to receive the accumulator vector and generate a post-processing output vector based on a post-processing instruction and the accumulator vector.