Merging Test Vectors to Reduce IC Simulation Compilation Time
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Solution Overview
Problem
Conventional IC design simulation systems require significant time for compiling, linking, and configuration due to the need for multiple test operations, which is inefficient as duplicate settings in test configurations lead to repetitive configuration operations.
Innovation Solution
Merging multiple test vectors into a single merged vector, where a common configuration is defined and modified only when necessary, allowing for independent simulation of test behaviors, thereby reducing the number of compilation, linking, and configuration steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple test vectors are processed separately through compiling and linking, then each test behavior can be simulated independently, but the time consumed for compiling, linking, and configuration is significant
Solution Approach 1:
The patent merges multiple test vectors into a single merged test vector that contains multiple operation sets. Instead of compiling and linking each test vector separately, the system compiles and links them together in one operation, reducing repetitive processing while maintaining the ability to simulate each test behavior independently through conditional branching
2Adaptability or versatility
If multiple test operations are performed with separate configurations, then each test can be executed independently, but the configuration and execution time increases significantly
Solution Approach 1:
The patent introduces dynamic conditional branching within the merged test vector. The system uses condition flags and branch instructions to dynamically select which operation sets to execute based on the current test state, allowing flexible adaptation to different test scenarios while avoiding repetitive configuration steps
3Manufacturing precision
If test vectors are compiled and linked individually, then the test configuration can be precise for each operation, but duplicate settings lead to repetitive configuration operations
Solution Approach 1:
The patent creates a universal merged test vector structure that can accommodate multiple different operation sets within a single configuration framework. Common configuration elements are defined once and reused across multiple operation sets, while specific test parameters can still be customized for each operation through the structured format
Data Source
AI summary
The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.