Mergeable Semiconductor Device Counter-Doped Body Region
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Solution Overview
Problem
High voltage transistor devices face degradation due to hot carrier injection and limited safe operating area, which limits their application and reliability, especially when merged for area savings, as conventional designs either suffer from unacceptably high degradation or poor safe operating area.
Innovation Solution
The implementation of a semiconductor device with a counter-doped drain-side body region and a drain extension depletion pocket, which reduces electric fields and enhances safe operating area without compromising mergeability or other performance parameters, by using existing implantation procedures to form a composite body region with nested wells and a depletion pocket.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If high voltage transistor devices are designed with features to prevent breakdown from high electric fields, then operating voltage is improved, but hot carrier injection degradation increases
Solution Approach 1:
The patent applies local quality by creating a counter-doped drain-side body region with different doping characteristics than the bulk body region. This localized doping modification reduces electric field concentration specifically at the drain boundary where hot carrier generation occurs, while maintaining high voltage operation capability in other regions of the device.
Solution Approach 2:
The patent changes the doping parameter of the body region at the drain side by introducing counter-doping with opposite polarity dopants. This parameter change modifies the electric field distribution and potential profile in the drain region, reducing hot carrier energy and injection into the gate oxide while preserving the overall high voltage operation characteristics.
2Area of stationary object
If transistor devices are merged within a common isolation ring to achieve area savings, then area is improved, but hot carrier injection degradation and safe operating area performance worsen
Solution Approach 1:
The patent applies local quality by implementing counter-doping specifically in the drain-side body region of each merged transistor device. This localized modification allows merged devices to maintain individual electric field control and hot carrier management capabilities while sharing a common body region, thereby preserving reliability performance despite area savings from merging.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves hot carrier injection immunity, safe operating area, and time-dependent dielectric breakdown performance, maintaining device reliability and mergeability while avoiding area penalties and mismatch issues.
Implementation Method 1
The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region.
Implementation Method 2
a pocket in the drain extension region, having the second conductivity type, and configured to establish a depletion region along an edge of the gate structure
Data Source
AI summary
A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.