Merged Active Area OTP Memory Layout Without Metal Routing
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Solution Overview
Problem
The routing of metallic interconnects in one-time-programmable (OTP) memory devices limits the reduction of minimum feature size and increases routing density, posing a challenge in the development of nonvolatile memory devices.
Innovation Solution
A memory device design that includes a semiconductor substrate with an isolation structure and active areas, where a fuse gate structure and a device gate structure are disposed over the active areas, allowing for signal transmission through the active area instead of a metallic interconnect, thereby reducing the occupied area by the metallic interconnect and the device gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metallic interconnect is used for signal transmission, then routing is achieved, but routing density increases and minimum feature size reduction is limited
Solution Approach 1:
The patent extracts and removes the metallic interconnect from the signal transmission path. Instead of using a metallic interconnect to route the signal from the contact plug to the fuse gate structure, the signal is transmitted directly through the active area of the semiconductive substrate. This extraction eliminates the routing complexity and allows for smaller feature sizes without increasing routing density.
2Ease of operation
If metallic interconnect is routed above semiconductive substrate, then signal transmission is achieved, but area occupied by metallic interconnect increases
Solution Approach 1:
The metallic interconnect is extracted and removed from the device structure. The signal transmission function previously performed by the metallic interconnect is now achieved through the active area of the substrate, eliminating the need for additional area to accommodate the metallic interconnect.
Solution Approach 2:
The active area of the semiconductive substrate is given multiple functions: it serves as both the active region for the fuse gate structure and the signal transmission path. This multi-functionality eliminates the need for separate metallic interconnect structures, reducing the overall area occupied by the device.
3Area of stationary object
If fuse gate structure and device gate structure are disposed adjacent to each other over active area, then space utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The fuse gate structure and device gate structure are merged and disposed adjacent to each other over the same active area. This merging allows both structures to share the same active area and manufacturing process steps, improving space utilization without significantly increasing manufacturing complexity.
Solution Approach 2:
Both the fuse gate structure and device gate structure are arranged in the same planar dimension over the active area, utilizing vertical stacking and lateral adjacency to maximize space utilization while maintaining compatibility with standard manufacturing processes.
Data Source
AI summary
The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.