Merged Bit Lines for High Density eFuse Memory Arrays
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Solution Overview
Problem
Embedded fuse (eFuse) memory macros face challenges with low density, large size, and the need for high programming voltages due to increased parasitic resistance in advanced nodes, which also induce voltage stress on devices.
Innovation Solution
The proposed solution involves merging bit lines and pass gates into a common bit line plane to reduce parasitic resistance, enabling a high-density eFuse by minimizing memory cell size and allowing for lower programming voltages, thus protecting transistors from voltage stress and simplifying chip design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If bit lines and pass gates are separate, then device control is simpler, but parasitic resistance increases
Solution Approach 1:
The patent merges bit lines and pass gates into a unified structure where the bit line serves dual functionality as both data transmission line and pass gate control line. This integration eliminates the separate pass gate component, reducing parasitic resistance by removing additional resistance paths while maintaining device control capabilities through the combined bit line structure.
2Quantity of substance
If memory cell size is reduced for high density, then eFuse density increases, but parasitic resistance increases
Solution Approach 1:
By combining bit line and pass gate functions into a single integrated structure, the patent reduces the overall number of conductive paths and contact points in the memory cell. This merging approach decreases parasitic resistance despite reduced cell size, as the integrated structure eliminates additional resistance interfaces that would otherwise be present in separate bit line and pass gate configurations.
3Power
If programming voltage is increased to overcome parasitic resistance, then program current increases, but voltage stress on transistors increases
Solution Approach 1:
The integrated bit line structure reduces parasitic resistance, which directly lowers the voltage drop across the bit line during programming operations. This reduced voltage drop allows the use of lower programming voltages to achieve the same program current, thereby reducing voltage stress on transistors while maintaining effective fuse programming capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic resistance in the memory cell program path, enables higher-density eFuses with smaller memory cells, lowers programming voltage, and protects transistors from voltage stress, making it suitable for advanced nodes with tighter design trade-offs.
Implementation Method 1
Large program current and/or power may be required to burn, via Joule heat or electron migration, fuse elements in an embedded fuse (eFuse) memory macro.
Implementation Method 2
Large program current and/or power may be required to burn, via Joule heat or electron migration, fuse elements in an embedded fuse (eFuse) memory macro.
Data Source
AI summary
In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.