Merged Control Gate Scaling for Split Gate Memory Cells
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Solution Overview
Problem
The challenge in scaling nonvolatile memory arrays lies in establishing effective contact between control gates and the active regions of the semiconductor substrate, particularly in forming a common control gate structure that is physically separated from multiple bitcells.
Innovation Solution
The method involves burying a source region within the active region of the semiconductor substrate and forming a merged control gate structure over this buried source region, allowing multiple bitcells to share a larger control gate, thereby enhancing contact area and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a common control gate structure is formed that is physically separated from multiple bitcells, then the gate area can be enlarged and multiple bitcells can share a control gate, but establishing contact with the active regions of the underlying substrate becomes difficult
Solution Approach 1:
The control gate structure extends in the vertical dimension by incorporating a plug that penetrates through the substrate thickness. This vertical extension allows the control gate to establish contact with active regions at different depths and locations, resolving the contact establishment difficulty while maintaining the enlarged gate area benefit
Solution Approach 2:
A plug structure acts as an intermediary element between the control gate and the active regions. The plug penetrates the substrate and provides a conductive pathway that enables electrical contact between the control gate and multiple separated active regions, solving the contact establishment problem
2Productivity
If memory arrays are scaled down, then device density increases, but establishing effective contact between control gates and active regions becomes more challenging
Solution Approach 1:
By extending the control gate structure vertically through substrate penetration, the invention enables effective contact establishment in scaled-down devices. The vertical dimension provides an additional pathway for contact that is independent of horizontal scaling, allowing device density to increase while maintaining manufacturable contact structures
Solution Approach 2:
The contact establishment is segmented into multiple independent plug structures, each penetrating to specific active regions. This segmentation allows flexible adaptation to scaled layouts where multiple small active regions need contact, enabling high device density while maintaining ease of manufacture through modular contact structures
Data Source
AI summary
A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.