Merged Data Stashing Control for Lower-Latency Processor Sharing
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Solution Overview
Problem
Existing data processing systems face significant latency and energy consumption issues due to memory access for data sharing between processing elements, and existing stashing mechanisms do not efficiently utilize bandwidth or reduce latency when multiple data updates are involved.
Innovation Solution
Implementing a merge buffer within a processing element to buffer updated data specified by a sequence of instructions, initiating a merged data update stashing transaction when a merging condition is no longer present, and using a merge end hint instruction to control the termination of the merging process, thereby optimizing bandwidth and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to memory to make it available to other processing elements, then data availability is improved, but latency and energy consumption increase
Solution Approach 1:
The patent introduces a merge buffer as an intermediary structure between the processing element and main memory. The merge buffer temporarily holds updated data blocks, allowing the data to be made available to other processing elements through the interconnect circuitry without requiring immediate main memory access. This intermediary buffer resolves the contradiction by providing fast local access (reducing latency) while maintaining data availability for stashing operations.
2Productivity
If multiple data update instructions are buffered in a merge buffer, then bandwidth utilization is improved, but data availability for stashing is delayed
Solution Approach 1:
The patent implements dynamic control of the merge buffer through a stashing-specific merge end trigger. Instead of a fixed buffering policy, the system dynamically adjusts when to flush buffered data based on stashing requirements. When stashing is needed, the trigger causes the merge buffer to flush its contents, ensuring data availability. This dynamic mechanism resolves the contradiction by adapting the buffering behavior to actual stashing needs, providing both high bandwidth utilization and timely data availability.
3Reliability
If data is immediately stashed without merging, then data availability is improved, but bandwidth utilization and power consumption worsen
Solution Approach 1:
The patent combines multiple data update instructions into a single merged data block before stashing. The merge buffer accumulates updates to the same address-aligned block, merging them into one consolidated write operation. This merging reduces the total number of stashing transactions, thereby reducing power consumption and improving bandwidth utilization while still ensuring data availability through the buffered merge operation.
4Productivity
If merging is performed for all data updates, then bandwidth utilization is improved, but latency for time-critical stashing operations increases
Solution Approach 1:
The patent implements a dynamic merge buffer flush mechanism triggered by stashing operations. When a stashing operation is required, the merge end trigger causes the merge buffer to flush its contents, prioritizing data availability over continued merging. This dynamic behavior allows the system to maintain high bandwidth utilization during normal operations while minimizing latency when stashing is needed, resolving the contradiction between merging benefits and stashing latency.
Data Source
AI summary
An apparatus has decoder circuitry within a first processing element to decode a sequence of instructions in order to generate control signals. Processing circuitry within the first processing element is responsive to the control signals to perform operations defined by the sequence of instructions. Whilst a merging condition is determined to be present, the processing circuitry is responsive to the control signals received from the decoder circuitry due to decoding N data update instructions that each specify updated data to be made available for stashing, where N is an integer greater than or equal to 1, to buffer the updated data specified by the N data update instructions. When the merging condition is determined to be no longer present, the processing circuitry issues a merged data update stashing transaction to interconnect circuitry specifying, as merged updated data, the updated data specified by the N data update instructions, in order to trigger stashing control circuitry accessible via the interconnect circuitry to cause the merged updated data to be made available for stashing in an associated storage structure of at least one further processing element. The processing circuitry is responsive to a stashing specific merge end trigger to determine that the merging condition is no longer present.