Merged Epitaxy Backside Cut for FET Parasitic Capacitance

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Solution Overview

Problem

As transistors shrink, merging source and drain epitaxial features of neighboring transistors becomes challenging, leading to insufficient separation and increased parasitic capacitance, which affects the performance of semiconductor devices.

Innovation Solution

The introduction of a silicon feature as a seed layer in shallow trench isolation regions or as a buried silicon feature allows for complete merger of source and drain epitaxial features before cutting, ensuring proper separation and reducing parasitic capacitance by using additional backside processing to fill openings with dielectric material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If transistors are shrunk to increase functional density, then production efficiency increases and costs decrease, but source and drain epitaxial features of neighboring transistors cannot be sufficiently separated, leading to increased parasitic capacitance

Engineering Contradiction:
Improveproduction efficiencyVSAvoidparasitic capacitance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a vertical dimension by forming a recess in the substrate and filling it with isolation material between neighboring transistors. This third-dimensional approach (going below the surface) enables separation of source and drain epitaxial features that cannot be achieved through lateral scaling alone, thereby reducing parasitic capacitance while maintaining high functional density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent uses an isolation material (such as silicon oxide or silicon nitride) as an intermediary substance filled in the substrate recess. This intermediary material physically separates the source and drain epitaxial features of neighboring transistors, preventing direct electrical interaction and reducing parasitic capacitance between them.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If source and drain epitaxial features are completely merged before cutting, then proper separation is achieved, but additional backside processing steps are required

Engineering Contradiction:
Improveseparation qualityVSAvoidprocessing steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by completely merging the source and drain epitaxial features before the cutting step. This ensures that when the substrate is subsequently cut into individual devices, proper separation is achieved. The merging is done in advance while the structure is still intact, making the separation process more reliable.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the processing into distinct stages: first merging the epitaxial features completely, then cutting the substrate, and finally forming the separated source and drain regions. This segmentation of the manufacturing process allows each step to be optimized independently, ensuring complete merger before separation.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces parasitic capacitance and improves lateral separation between source and drain epitaxial features, enhancing the performance and reliability of semiconductor devices.

Implementation Method 1

forming a merged source/drain region over the first fin, the second fin and the third fin

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20240379803A1Field effect transistor with merged epitaxy backside cut and method
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379803A1 patent drawing
  • US20240379803A1 patent drawing
  • US20240379803A1 patent drawing

AI summary

A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.