Merged Epitaxy Fin Structure for Dense SRAM Stability
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating high-density, high-performance SRAM cells with FinFETs due to complexities in manufacturing and design, particularly in maintaining stable logic states without refresh cycles and achieving optimal packing densities in integrated circuits.
Innovation Solution
The use of FinFETs in SRAM cells, where semiconductor fins are formed on a substrate with specific well regions and gate stacks, and epitaxy structures are grown within recesses, with dielectric fin sidewall structures adjusting epitaxy growth to enhance carrier mobility and device performance, allowing for stable logic states and increased packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistors are used, then manufacturing is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional FinFET structures with vertical channels. The fin extends upward from the substrate, creating a vertical channel that allows gate control from multiple directions (front and back gates), effectively adding a dimensional aspect to the transistor architecture to achieve higher device density
2Productivity
If FinFET structures are implemented, then device density and performance improve, but manufacturing complexity increases
Solution Approach 1:
The FinFET structure is divided into multiple independently controllable gates (front gate and back gate) that can be formed and controlled separately. This segmentation allows for independent optimization of each gate's function and simplifies the manufacturing process by breaking down the complex three-dimensional structure into manageable fabrication steps
Solution Approach 2:
The patent forms the fin structure and first gate before creating the second gate, establishing a sequential fabrication process. This preliminary action of forming the vertical fin and initial gate structure provides a foundation that simplifies subsequent manufacturing steps, allowing for better control over the final device geometry and performance characteristics
3Productivity
If higher device density is achieved through vertical fins, then packing density improves, but maintaining stable logic states becomes more challenging
Solution Approach 1:
The patent implements a dual-gate FinFET structure where both the front gate and back gate can independently control the channel, providing multi-functional control over device operation. This universal control mechanism allows for enhanced threshold voltage control and better maintenance of stable logic states through coordinated gating, addressing the reliability challenges associated with high-density vertical structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable data retention in SRAM cells without refresh cycles and improves packing density by optimizing the structure and growth of epitaxy and dielectric fin sidewall structures, enhancing the performance and efficiency of SRAM devices.
Implementation Method 1
epitaxy structures are grown within recesses, with dielectric fin sidewall structures adjusting epitaxy growth to enhance carrier mobility
Data Source
AI summary
A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.