Merged FinFET Source-Drain Epitaxial Growth
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Solution Overview
Problem
FinFETs face increased parasitic resistance as fin width is scaled down, which existing technologies have not effectively mitigated.
Innovation Solution
The method involves forming silicon fins on a silicon substrate with a thin buried oxide layer, growing epitaxial silicon from the substrate and fin ends to create merged source/drains, thereby reducing parasitic resistance and capacitance by minimizing total source-drain height and promoting vertical epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If fin width is scaled down to improve device density and integration, then device scaling is achieved, but parasitic resistance increases
Solution Approach 1:
The patent transitions from planar source/drain structures to vertically merged source/drain structures. By growing epitaxial silicon vertically from the substrate up the fin sidewalls and merging at the top, the current path is extended in the vertical dimension rather than remaining confined to the horizontal plane. This dimensional change allows current to flow through a larger cross-sectional area at the merged region, reducing parasitic resistance even as fin width is scaled down.
Solution Approach 2:
The patent employs a composite structure combining the original fin silicon with epitaxially grown silicon regions. The merged source/drain structure integrates the substrate region, fin sidewall regions, and epitaxial growth regions into a unified composite structure. This composite approach allows optimization of each region's properties while achieving overall reduced parasitic resistance through the merged configuration.
2Object-affected harmful factors
If source-drain height is increased to reduce parasitic resistance, then parasitic resistance decreases, but crystal lattice irregularities and induced stress increase
Solution Approach 1:
The patent performs preliminary epitaxial growth on the fin sidewalls before final merging. By growing the epitaxial silicon layers conformally on the sidewalls first, the crystal structure is established in a controlled manner that promotes lattice alignment. This preliminary structuring prevents random crystal orientation and reduces lattice irregularities that would otherwise occur with uncontrolled vertical growth.
Solution Approach 2:
The patent controls the epitaxial growth parameters including temperature, pressure, and gas flow rates to optimize crystal quality. By carefully adjusting these parameters during the epitaxial process, the growth rate and crystal orientation are controlled to minimize lattice defects and stress while achieving the desired merged source/drain height for reducing parasitic resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases parasitic resistance and capacitance, making finFETs more efficient as fin sizes decrease, while minimizing crystal lattice irregularities and induced stress in the channels.
Implementation Method 1
simultaneously growing epitaxial silicon from the first and second regions of the substrate and from the first and second ends of the central regions of each fin of the two or more fins to form respective first and second merged source/drains
Data Source
AI summary
A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.