Merged Frame Rate Converter and Video Codec SoC
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Solution Overview
Problem
The increasing demand for high-definition video services with high resolution, high frame rate, and high bit-depth poses a challenge in minimizing the cost and size of components such as video codecs and frame rate converters in mobile devices, as existing systems require larger hardware to support these demands.
Innovation Solution
A system-on-chip that merges a video codec with a frame rate converter, incorporating a motion estimator, motion compensator, and parameter generator, which uses deblocking and self-guided filters to perform frame rate conversion and noise reduction, thereby sharing components and reducing chip area and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If separate hardware components are used for video codec and frame rate converter, then functional performance is maintained, but chip area and manufacturing cost increase
Solution Approach 1:
The patent merges the frame rate converter and video codec into a single integrated component, sharing common hardware resources such as motion estimation units, motion compensation units, and deblocking filters. This consolidation reduces the total chip area while maintaining both frame rate conversion and video decoding functionalities through unified resource allocation and mode switching mechanisms.
Solution Approach 2:
The integrated component is designed to perform multiple functions by sharing hardware resources between frame rate conversion and video decoding operations. The motion estimator and motion compensator serve both frame interpolation and video compression tasks, while the deblocking filter processes both decoded video and interpolated frames, achieving multi-functionality without sacrificing performance in either domain.
2Productivity
If high-definition video services with high resolution and high frame rate are supported, then service quality is improved, but component size and cost increase
Solution Approach 1:
The patent integrates frame rate conversion capabilities into the video codec, enabling high frame rate output from lower frame rate input videos. The shared motion compensation unit generates intermediate frames for high frame rate display while maintaining high resolution quality, and the integrated deblocking filter ensures quality output without requiring separate high-performance components.
Solution Approach 2:
The system dynamically adjusts processing parameters such as motion vector precision, interpolation filter strength, and deblocking filter levels based on the operating mode (frame rate conversion vs. standard decoding) and content characteristics. This allows the integrated component to optimize performance for high-definition high frame rate services while efficiently managing the limited hardware resources available.
Data Source
AI summary
A system-on-chip which includes a video codec including a deblocking filter includes a motion estimator that calculates a motion vector of an input image, a motion compensator that compensates for a motion of the input image by using the motion vector, and a parameter generator that allows image data, in which the motion is compensated, to be transferred to and filtered by the deblocking filter of the video codec.