Merged Gate and Source/Drain Contacts in FinFET Devices
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Solution Overview
Problem
Current approaches for forming contacts in FinFET devices face challenges such as high contact resistance, partial coverage of fin edges, and degraded critical dimensions due to tapered contact shapes and stringent overlay requirements, leading to yield issues and design complexities at 14 nm and smaller dimensions.
Innovation Solution
The method involves forming a dielectric layer over gate structures, patterning source/drain openings, and depositing a deep ultraviolet light absorbing oxide fill material, followed by selective removal of the fill material and deposition of metal to create merged gate and source/drain contacts, which allows for improved contact stitching and reduced critical dimension degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If replacement metal contact scheme is used for S/D contacts at 10XM dimensions, then overlay requirements are relaxed, but processing of gate contact before S/D contact is prevented and critical dimension degrades
Solution Approach 1:
The merged contact structure is formed as a single unit that contacts both gate and source/drain regions. This unified contact can be processed in a single step using conventional lithography and etching, eliminating the need for replacement metal schemes. The single-contact geometry maintains critical dimensions while allowing flexible processing sequences, including the ability to form gate contacts before S/D contacts if desired.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of merged contacts with reduced contact resistance and improved yield by allowing for direct electrical connection of gate and source/drain contacts, maintaining critical dimension integrity and addressing the challenges of partial coverage and yield issues.
Implementation Method 1
forming a fill material (e.g., a deep ultraviolet light absorbing oxide) formed over the gate structures, including within the S/D openings
Data Source
AI summary
Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.