Merged Gate Vertical Transistor Self-Aligned Sidewall Image Transfer
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Solution Overview
Problem
The challenge in fabricating vertical FET structures with high aspect ratios is exacerbated by overlay errors in traditional lithography techniques, which hinder the formation of thin, merged gate structures necessary for increased device density.
Innovation Solution
The implementation of a self-aligned sidewall image transfer (SIT) technique, coupled with the use of a protective structure during gate etching, ensures the integrity of merged gate regions, allowing for the formation of thin, high aspect ratio gates with sufficient area for merged gate contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography techniques are used to fabricate vertical FET structures, then the manufacturing process is simpler, but overlay errors prevent the formation of thin merged gate structures with high aspect ratios
Solution Approach 1:
The patent applies preliminary action by forming spacer structures before the gate etching process. These spacers are deposited conformally on the fin structures and then patterned to define the merged gate region boundaries. This preliminary spacer formation establishes self-aligned references that guide subsequent etching, ensuring precise gate thickness and merged gate formation without relying on overlay-critical lithography steps at this stage.
Solution Approach 2:
The patent introduces spacer structures as intermediary elements that mediate between the lithography pattern and the final gate structure. These spacers act as self-aligned masks and etch stop layers, transferring the pattern definition from lithography to the gate region with high precision. The spacers serve as intermediate structures that protect certain regions during etching while defining the merged gate boundaries, thereby achieving high aspect ratio gates without direct lithographic patterning of the gate itself.
2Productivity
If thin merged gate structures are formed to increase device density, then device density increases, but overlay errors compromise the integrity of the merged gate regions
Solution Approach 1:
The patent implements self-service through self-aligned spacer formation and etching processes. The spacers are deposited conformally on the fin structures, automatically positioning themselves relative to the fins without requiring additional lithography alignment. During etching, the spacers serve as their own masks, defining the merged gate regions through their physical presence rather than through lithographically-defined patterns. This self-alignment mechanism eliminates overlay errors that would otherwise compromise merged gate integrity.
Solution Approach 2:
The patent applies preliminary anti-action by forming protective spacer structures before the gate etching process that prevent etching in the merged gate regions. These spacers are strategically positioned to protect the areas where merged gates will form, counteracting the potential harmful effect of overlay errors during etching. The spacers pre-establish protection zones that ensure merged gate region integrity regardless of lithography overlay variations.
3Area of moving object
If high aspect ratio gate structures are fabricated, then device density increases, but the fabrication process becomes more difficult due to overlay errors
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional self-aligned spacer formation and etching. Instead of defining gate patterns directly through planar lithography, the process uses vertical spacer deposition on fin structures, followed by anisotropic etching. This dimensional transition from 2D pattern transfer to 3D self-aligned formation enables high aspect ratio gates while reducing sensitivity to lithography overlay errors, as the critical dimensions are determined by spacer thickness and etch selectivity rather than lithographic resolution.
Data Source
AI summary
Embodiments of the invention are directed to a semiconductor structure that includes a first fin structure having a first sidewall, a first gate structure adjacent a lower portion of the first sidewall, and a first spacer structure over the first gate structure and adjacent an upper portion of first the sidewall. The first spacer structure includes a first spacer structure thickness dimension that extends in a first direction away from the first sidewall. The first gate structure includes a first gate structure thickness dimension that extends in the first direction away from the first sidewall. The first gate structure dimension is about equal to the first spacer structure thickness dimension.