Merged Memory Banks with Segmented Row Access
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Solution Overview
Problem
Existing memory devices with merged memory banks face challenges in increasing memory bandwidth while maintaining low bank overhead and achieving truly independent sub-bank access.
Innovation Solution
The proposed memory device structure includes memory banks merged on a substrate with row segments acting as pseudo-independent banks, and memory peripheral circuitry components disposed outside the substrate to reduce overhead. This structure allows for independent sub-bank access and increased memory bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If memory banks are merged on substrate to reduce overhead, then bank overhead is reduced, but memory bandwidth is limited
Solution Approach 1:
The memory array is divided into multiple row segments that can be independently activated. Each row segment functions as a pseudo-independent bank with its own sense amplifier circuit, enabling parallel access to multiple segments simultaneously. This segmentation allows the system to achieve high memory bandwidth while maintaining low bank overhead by reducing the number of fully independent banks needed.
Solution Approach 2:
Multiple memory banks are merged on a single substrate with shared peripheral circuitry. The row segments share common row decoders and control signals, reducing the overall device complexity and bank overhead. Despite sharing resources, the segments can be activated independently to provide high bandwidth performance.
2Productivity
If multiple independent banks are implemented to increase bandwidth, then memory bandwidth is increased, but bank overhead increases
Solution Approach 1:
Instead of creating multiple fully independent banks with separate peripheral circuitry, the memory is segmented into row segments that share common resources. Each row segment has dedicated sense amplifier circuits but shares row decoders and control logic, reducing overhead while maintaining parallel access capability for high bandwidth.
Solution Approach 2:
The row decoders and control circuitry serve multiple row segments simultaneously, making them universal components that perform the same function across different segments. This multi-functionality reduces the total number of components needed while maintaining the ability to access multiple segments in parallel for high bandwidth operation.
3Device complexity
If row segments share sense amplifier circuits, then device complexity is reduced, but independent access to neighboring segments is blocked
Solution Approach 1:
The sense amplifier circuits are dynamically controlled to serve different row segments at different times. When one segment is activated, its neighboring segments are kept inactive, and the sense amplifiers are enabled for the active segment. This dynamic control allows sharing of sense amplifier circuits while maintaining the ability to independently access any segment when needed.
Solution Approach 2:
Before activating a row segment, the control logic ensures that neighboring segments are pre-charged and placed in a known inactive state. This preliminary action prepares the shared sense amplifier circuits to be exclusively available for the upcoming segment access, enabling independent access despite sharing.
Data Source
AI summary
A memory device includes one or more memory blocks. Each memory block includes a plurality of first sense amplifier circuits, a plurality of row segments, and a plurality of row decoders. The row segments and the first sense amplifier circuits are arranged alternately along a first direction. Each row segment includes a plurality of memory cells arranged in rows and columns. Each column of memory cells extends in the first direction. The row segments are divided into N groups of row segments, and N is greater than one. The row decoders are coupled to the row segments respectively, and divided into N groups of row decoders.