Merged DRAM Commands to Reduce Command Bus Congestion

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Solution Overview

Problem

Existing memory systems face congestion on the command bus due to the frequent transmission of separate precharge, refresh, and activate operations, leading to reduced performance and increased power consumption, particularly in dynamic random access memory (DRAM) systems.

Innovation Solution

Implementing merged memory commands that combine precharge, refresh, and activate operations into a single command, reducing the number of commands sent over the command bus and optimizing bus utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate precharge, refresh, and activate commands are transmitted over the command bus, then each operation can be performed independently and reliably, but command bus congestion increases and performance decreases

Engineering Contradiction:
Improveoperation reliabilityVSAvoidmemory performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent combines multiple memory operations (precharge, refresh, activate) into a single merged command that can be transmitted over the command bus in one transaction. This merging reduces the number of separate commands needed, thereby reducing bus congestion and improving memory performance while maintaining the reliability of each individual operation through proper sequencing and control logic within the memory controller

Inventive Principle:
Principle #5Merging (Combining)

2Ease of operation

If multiple separate commands are sent for precharge, refresh, and activate operations, then each operation can be precisely controlled, but the number of commands increases and bus bandwidth is wasted

Engineering Contradiction:
Improveoperation control precisionVSAvoidnumber of commands
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent merges multiple control operations into a single command structure that includes fields for specifying precharge, refresh, and activate operations. This reduces the quantity of commands transmitted over the bus while maintaining precise control through the command's embedded operation codes and parameters that define the specific actions to be performed on memory banks and rows

Inventive Principle:
Principle #5Merging (Combining)

3Speed

If frequent separate commands are transmitted for memory operations, then real-time control is achieved, but power consumption increases

Engineering Contradiction:
Improvecontrol response speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent reduces power consumption by merging multiple memory operations into a single command transmission event. Since command transmissions are a major source of power consumption in memory systems, consolidating precharge, refresh, and activate operations into one command reduces the frequency of transmissions and associated power usage, while the memory controller maintains real-time control capability through efficient command parsing and execution

Inventive Principle:
Principle #5Merging (Combining)

4Device complexity

If separate commands are used for each memory operation, then command processing is straightforward, but command bus congestion increases and bandwidth is reduced

Engineering Contradiction:
Improvecommand processing simplicityVSAvoidbus utilization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent improves bus utilization by merging multiple operations into a single command that occupies only one command bus transaction. Although the command structure is more complex internally, the overall system benefits from reduced bus congestion and higher throughput, as the merged command replaces what would otherwise require multiple separate command transmissions, thereby freeing up bus bandwidth for other operations

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250217051A1Merged memory commands for improved bus utilization in volatile memory
Publication Date: 2025.07.03 QUALCOMM INC
  • US20250217051A1 patent drawing
  • US20250217051A1 patent drawing
  • US20250217051A1 patent drawing

AI summary

This disclosure provides systems, methods, and devices for memory systems that support merged memory commands for improved bus utilization in volatile memory. In a first aspect, a method of performing operations on a memory module includes receiving, from a host device by a memory controller coupled to a memory module through a first channel and configured to access data stored in the memory module through the first channel, a merged command for performing at least a precharge operation, a refresh operation, and an activate operation on one or more rows of the memory module and performing the precharge operation, the refresh operation, and the activate operation in accordance with receipt of the merged command. Other aspects and features are also claimed and described.