Merged Metal Pattern Layout for Double Patterning Overlay Errors
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Solution Overview
Problem
The double patterning technique in semiconductor manufacturing faces challenges with overlay control and alignment, leading to issues such as broken lines and merged connections, which result in open or short circuits due to inaccuracies in the decomposition of high-density circuit patterns into lower density patterns.
Innovation Solution
A semiconductor structure and method that includes a substrate with metal patterns and merged patterns, where the merged patterns are designed with specific geometries such as misaligned short axes, recessed and protruded regions, and offset portions to mitigate alignment errors during photolithography, ensuring accurate pattern transfer and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-density circuit patterns are decomposed into two or more sets of lower density patterns for double patterning, then the minimum pattern distance can be enlarged to fit present mask aligner capabilities, but overlay control and alignment accuracy deteriorate, leading to disconnection or connection of circuit patterns
Solution Approach 1:
The patent introduces dummy patterns around critical circuit patterns before the decomposition process. These dummy patterns are pre-positioned to compensate for anticipated overlay errors during subsequent exposure processes. By performing this preliminary action, the system proactively addresses alignment issues that would otherwise occur during the double patterning process, maintaining both enlarged minimum pattern distances and acceptable overlay control.
Solution Approach 2:
The dummy patterns act as intermediary elements between the decomposed circuit patterns. During exposure, these intermediary dummy patterns help define the boundaries and positions of adjacent patterns, serving as reference features that improve overlay control. The dummy patterns mediate the alignment relationship between different exposure steps, reducing the direct dependency on precise alignment between decomposed patterns.
2Length of moving object
If multiple exposure processes are used in double patterning to fabricate high-density circuit patterns, then the line width can be reduced to 32 nm to 22 nm, but the complexity of overlay control and alignment increases significantly
Solution Approach 1:
The dummy patterns are designed and positioned in advance based on the known decomposition scheme and anticipated overlay errors. This preliminary design phase captures the complexity management, allowing the actual multiple exposure processes to proceed with simpler alignment requirements. The pre-planned dummy pattern positions serve as built-in alignment references that reduce the operational complexity during exposure.
Solution Approach 2:
The dummy patterns are designed to be self-aligning with the circuit patterns through geometric relationships and spacing rules. During exposure, the dummy patterns automatically serve their alignment function without requiring additional alignment procedures or complex control mechanisms. The system uses the dummy patterns' inherent geometric properties to self-correct alignment issues, reducing the need for external overlay control complexity.
Data Source
AI summary
A semiconductor structure, including a plurality of metal patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the metal patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and one short axis of the first outer line, one short axis of the central line and one short axis of the second outer line are misaligned along the first direction.