Merged Mode Timing Constraints for Electronic Circuits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The complexity of electronic circuit designs and the need for repeated timing analysis across various modes and corners result in high computational costs and error-prone manual merging of modes, making it inefficient and costly to verify timing performance.

Innovation Solution

A computer-implemented method for automatically generating and verifying merged mode constraints by combining timing constraints from individual modes, identifying and eliminating extraneous timing relationships, and adding necessary constraints to ensure equivalence with individual modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual merging of modes is performed to reduce the number of scenarios, then the number of timing analysis combinations is reduced, but the process becomes error-prone and costly due to complexity of constraints

Engineering Contradiction:
Improvenumber of timing analysis combinationsVSAvoidcorrectness of merged modes
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs automatic self-verification of merged modes by comparing timing relationships against individual mode constraints, eliminating the need for manual verification and reducing errors

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements feedback mechanisms where merged mode constraints are automatically verified against original individual modes, and corrections are made based on verification results to ensure correctness

Inventive Principle:
Principle #23Feedback

2Loss of time

If individual timing constraints from multiple modes are combined into merged modes, then the number of scenarios to verify is reduced by 90%, but extraneous timing relationships may be introduced

Engineering Contradiction:
Improvetime for timing analysisVSAvoidaccuracy of timing relationships
Core Design Contradiction:
Loss of timeVSManufacturing precision

Solution Approach 1:

The system extracts and identifies extraneous timing relationships from merged modes by comparing against individual mode constraints, and removes these extraneous relationships to maintain accuracy

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system modifies the merged mode constraints by adding specific constraints that eliminate extraneous timing relationships, transforming the merged mode to achieve both reduction and accuracy

Inventive Principle:
Principle #35Parameter changes

3Reliability

If manual verification of merged modes against individual modes is performed, then confidence in correctness may be improved, but the cost and time become prohibitive due to large number of constraints

Engineering Contradiction:
Improveconfidence in merged modesVSAvoidcost of verification
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The verification system performs automatic self-checking of merged modes against individual modes, eliminating the need for expensive manual verification while maintaining high confidence

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system replaces manual verification processes with automated computer-based verification, substituting human effort with algorithmic processing to reduce costs

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8627262B2Automatic generation of merged mode constraints for electronic circuits
Publication Date: 2014.01.07 SYNOPSYS INC
  • US8627262B2 patent drawing
  • US8627262B2 patent drawing
  • US8627262B2 patent drawing

AI summary

Individual mode timing constraints associated with a set of netlists are combined into merged mode timing constraints. An initial merged mode constraint is generated by combining timing constraints from individual modes. The initial merged mode includes the union of all timing constraints from individual modes that add timing relationships and the intersection of all timing constraints from the individual modes that remove timing relationships. Extraneous timing relationships are identified in the merged mode and eliminated by introducing timing constraints in the merged mode. Equivalence between the merged mode and the individual modes is verified by comparing timing relationships in the merged mode with timing relationships in the individual modes. The merged mode is considered equivalent to the individual modes if every timing relationship present in an individual mode is present in the merged mode and every timing relationship present in the merged mode is present in any of individual modes.