Merged Split N-Well Cell Layout for Multi-Voltage IC Area Reduction
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Solution Overview
Problem
Existing integrated circuit (IC) designs face inefficiencies due to wasted circuit area and increased size from split N-well cells, which do not effectively utilize space and require multiple power supply routings for different voltage levels.
Innovation Solution
Implementing a merged split N-well cell design that integrates multiple logic sub-blocks within a single N-well, reducing wasted area and optimizing power supply routing by connecting logic sub-blocks to a common node, thereby reducing circuit area and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If split N-well cells are used to support multiple voltage levels, then multiple voltage levels can be supported, but circuit area increases and space utilization deteriorates
Solution Approach 1:
The patent merges multiple N-well structures into a shared common N-well region. Instead of having separate N-wells for each logic sub-block, the invention combines them into a single continuous N-well that serves multiple voltage domains, thereby reducing the total circuit area while maintaining support for multiple voltage levels.
Solution Approach 2:
The common N-well structure serves multiple functions simultaneously: it provides the N-well region for multiple logic sub-blocks, supports multiple voltage levels through selective electrical connections, and acts as a shared substrate for both first and second power rails. This multi-functionality eliminates the need for separate dedicated N-wells for each function.
2Adaptability or versatility
If separate N-wells are used for different logic sub-blocks, then each sub-block can be independently configured, but manufacturing complexity and costs increase
Solution Approach 1:
The patent combines multiple N-well structures into a single common N-well region that is shared by multiple logic sub-blocks. This merging reduces the number of separate fabrication steps and simplifies the manufacturing process while still allowing each logic sub-block to be independently configured through selective electrical connections to different power rails.
3Adaptability or versatility
If multiple power supply routings are implemented for different voltage levels, then multiple voltage levels are supported, but routing resources and circuit complexity increase
Solution Approach 1:
The common N-well structure serves as a universal platform that can be selectively connected to different power rails (first power rail for first voltage level, second power rail for second voltage level). This allows the same physical structure to support multiple voltage levels without requiring separate dedicated routing for each voltage domain, thereby reducing routing complexity.
Data Source
AI summary
An N-well cell stored as a digital representation with a non-transitory computer readable medium. The N-well cell is used within a circuit block of an integrated circuit device. The N-well cell includes a first N-well electrically connected to a first power rail providing a first supply voltage. The first N-well further includes a second N-well electrically connected to the first power rail, and a third N-well electrically connected to a second power rail providing a second supply voltage different from the first supply voltage. The third N-well is positioned between the first N-well and the second N-well. The third N-well includes a first logic sub-block electrically connected to the second power rail, and a second logic sub-block electrically connected to the second power rail.