Merged Pixel and Memory Image Sensor Architecture
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Solution Overview
Problem
Existing image sensors with stacked semiconductor chips face challenges in miniaturization and low power consumption due to the need for separate chips for pixel arrays, logic circuits, and memory cell arrays, leading to inefficient communication and increased area and power usage.
Innovation Solution
A merged image sensor design where a first semiconductor chip includes both a pixel array and a memory cell array, with a second semiconductor chip overlapping the first in a vertical direction, containing logic circuits to control the pixel array and convert analog signals to digital for storage in the memory cell array, optimizing internal wiring and reducing the need for external communication paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If pixel array, logic circuit, and memory cell array are formed in separate semiconductor chips, then each chip can be optimized independently, but the communication between chips increases area and power consumption
Solution Approach 1:
The patent merges the pixel array and memory cell array into a single first semiconductor chip, eliminating the need for separate memory chips and reducing inter-chip communication. This combination reduces the number of external communication paths while maintaining independent optimization capabilities within the integrated structure.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked architecture where the pixel array and memory cell array are vertically arranged on the same chip. This vertical integration reduces the horizontal area required while maintaining functional separation, thereby reducing power consumption without sacrificing manufacturing independence.
2Ease of manufacture
If pixel array, logic circuit, and memory cell array are formed in separate semiconductor chips, then each chip can be optimized independently, but the communication between chips increases area and power consumption
Solution Approach 1:
The patent combines the pixel array and memory cell array on the same first semiconductor chip, eliminating the need for separate memory chips. This integration reduces the total area required for the image sensor while maintaining the ability to independently optimize each functional block during the design phase.
Solution Approach 2:
The patent employs a three-dimensional stacked architecture where components are arranged vertically on the same chip rather than spreading them out horizontally. This vertical integration significantly reduces the total area occupied by the image sensor while preserving independent optimization capabilities for each functional block.
3Use of energy by moving object
If pixel array and memory cell array are merged in the same semiconductor chip, then area and power consumption are reduced, but the complexity of integrating different functions increases
Solution Approach 1:
The patent segments the image sensor into distinct functional blocks (pixel array, memory cell array, logic circuits) that are vertically stacked on separate layers of the same chip. This segmentation allows each block to be independently designed and optimized while maintaining manageable integration complexity through clear functional separation.
Solution Approach 2:
The patent resolves integration complexity by arranging different functional blocks in the vertical dimension rather than mixing them horizontally. This three-dimensional stacking allows complex functions to be integrated while maintaining clear separation between blocks, making the design and manufacturing process more manageable despite the increased functional integration.
4Area of stationary object
If pixel array and memory cell array are merged in the same semiconductor chip, then area and power consumption are reduced, but the complexity of integrating different functions increases
Solution Approach 1:
The patent divides the image sensor into distinct functional segments (pixel array, memory cell array, logic circuits) arranged in vertical layers. This segmentation enables area reduction through compact stacking while keeping integration complexity manageable by maintaining clear functional boundaries and independent optimization paths for each segment.
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking, allowing multiple functional blocks to coexist on the same chip with minimal horizontal overlap. This dimensional change reduces total area while managing integration complexity through vertical layering and clear functional separation between layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances miniaturization and reduces power consumption by integrating control circuits within the same chip stack, improving the area and power efficiency of the image sensor.
Implementation Method 1
a photoelectric conversion unit configured to convert incident light into an electrical signal
Data Source
AI summary
An image sensor in which a pixel array and a memory cell array are merged includes a first semiconductor chip including the pixel array and the memory cell array in a same semiconductor chip, and a second semiconductor chip overlapping the first semiconductor chip in a vertical direction. The second semiconductor chip includes a first logic circuit that controls the pixel array, an analog-to-digital converter (ADC) that converts an analog signal output from the pixel array under control of the first logic circuit to a digital signal, and a second logic circuit that stores data that is output from the ADC circuit based on the digital signal to the memory cell array of the first semiconductor chip.