Merged Reset Write Operation for STT-RAM Latency Reduction
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Solution Overview
Problem
Magnetoresistive memory devices, such as STTRAM, face challenges with asymmetrical write performance, where writing to one bit state is significantly longer than writing to another, leading to increased write energy and time, and existing solutions either compromise persistence or rely on early termination, which do not effectively improve overall write latency.
Innovation Solution
Implementing a merged reset write operation that simultaneously resets multiple cachelines to the slower bit state and then selectively writes the faster bit state, reducing overall write time by amortizing the performance cost of writing the slower bit state across multiple operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If writing to the slower bit state is performed individually for each cacheline, then write accuracy and persistence are maintained, but overall write latency increases significantly
Solution Approach 1:
The patent merges multiple cacheline write operations into a single batch operation. When multiple cachelines need to be written to the slower bit state, they are combined into one unified write operation that processes all cachelines simultaneously, thereby amortizing the high write time cost across multiple cachelines and significantly reducing overall write latency while maintaining write persistence.
Solution Approach 2:
The patent performs preliminary grouping of cachelines that need to be written to the slower bit state before executing the write operation. By identifying and batching multiple cachelines in advance that require the same slow write operation, the system prepares the work in advance so that the expensive write operation is performed once for multiple cachelines rather than repeatedly for each cacheline individually.
2Loss of energy
If early termination is used to stop write operations after detection of cell switching, then unnecessary current flow is prevented, but worst case write latency remains unchanged
Solution Approach 1:
The patent merges multiple cacheline write operations into a single batch operation. When multiple cachelines need to be written to the slower bit state, they are combined into one unified write operation that processes all cachelines simultaneously, thereby amortizing the high write time cost across multiple cachelines and significantly reducing overall write latency while maintaining write persistence.
3Manufacturing precision
If multiple cachelines are written individually to the slower bit state, then each cachline is written accurately, but the total write time increases linearly with the number of cachelines
Solution Approach 1:
The patent merges multiple cacheline write operations into a single batch operation. When multiple cachelines need to be written to the slower bit state, they are combined into one unified write operation that processes all cachelines simultaneously, thereby amortizing the high write time cost across multiple cachelines and significantly reducing overall write latency while maintaining write persistence.
Data Source
AI summary
In a memory device where writing a memory cell to a first bit state takes longer than writing to the second bit state, selectively executing the write operation can amortize the performance cost of writing the bit state that takes longer to write. Write logic dequeues multiple cachelines from a write buffer and sets all bits of all cachelines to the first bit state in a single write operation. The write logic then executes separate write operations on each cacheline separately to selectively write memory cells of each respective cacheline to the second bit state.