Merged Source/Drain Epitaxy for Lower FinFET Capacitance
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Solution Overview
Problem
Conventional FinFET structures face challenges in reducing parasitic capacitance and contact resistance due to increased complexity and scaling down, which affects the performance of semiconductor devices.
Innovation Solution
A method is introduced to form source/drain features with multiple epitaxial layers, including a bar-like epitaxial layer to reduce the projection area on the gate structure and a conformal epitaxial layer to create a flat top surface, thereby reducing parasitic capacitance and contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FinFET structures are used with scaling down, then device density and production efficiency are improved, but parasitic capacitance between source/drain feature and gate increases
Solution Approach 1:
The source/drain feature transitions from a conventional planar structure to a multi-layer three-dimensional structure with a bar-like epitaxial layer and conformal epitaxial layer. This dimensional change reduces the projection area on the gate structure, thereby reducing parasitic capacitance while maintaining vertical integration for high device density
Solution Approach 2:
The source/drain feature is formed as a composite structure with multiple epitaxial layers (bar-like epitaxial layer and conformal epitaxial layer) having different compositions and properties. This composite structure optimizes both the electrical performance (reducing parasitic capacitance) and the manufacturing process requirements
2Productivity
If conventional FinFET structures are used with scaling down, then device density and production efficiency are improved, but contact resistance between source/drain feature and recessed fins increases
Solution Approach 1:
The source/drain feature adopts a multi-layer three-dimensional structure that extends vertically and horizontally, creating multiple contact interfaces with the recessed fins. This dimensional expansion increases the contact area and improves electrical contact reliability
Solution Approach 2:
The conformal epitaxial layer is formed over the bar-like epitaxial layer, creating a nested multi-layer structure. This nested configuration allows the source/drain feature to maintain intimate contact with the recessed fins while reducing the projection area on the gate
3Object-generated harmful factors
If source/drain feature projection area on gate structure is reduced, then parasitic capacitance is reduced, but contact area with source/drain contact may be insufficient
Solution Approach 1:
The source/drain feature is designed as a multi-layer structure where the projection area on the gate is reduced (lower layers) while the top surface area for contact (upper layers) is maintained or enhanced. This dimensional differentiation simultaneously reduces parasitic capacitance and ensures adequate contact area
Solution Approach 2:
Different regions of the source/drain feature have different geometries: the lower portion has a reduced projection area to minimize parasitic capacitance, while the top portion has an enlarged area to ensure adequate contact with source/drain contacts. This local quality variation optimizes both requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance and contact resistance, enhancing the performance of semiconductor devices by minimizing the projection area of source/drain features on the gate structure and facilitating better contact with the source/drain contact.
Implementation Method 1
The scaling down of FinFETs introduces challenges to reduce parasitic capacitance between the source/drain feature and the gate
Implementation Method 2
The scaling down of FinFETs introduces challenges to reduce parasitic capacitance between the source/drain feature and the gate and to lower resistance between the source/drain feature and the recessed fins
Data Source
AI summary
The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.