Merged TSV Layout for Lower Resistance Without Area Growth
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Solution Overview
Problem
Existing TSV layouts face challenges in reducing resistance without increasing chip area, as buffer zones limit the lateral dimensions of TSVs, making it difficult to form large TSVs and thereby increasing resistance.
Innovation Solution
Merging closely located TSVs and their guard rings into larger structures while maintaining the same chip area, adhering to design rules, thereby reducing resistance without expanding the chip's footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV lateral dimensions are increased to reduce resistance, then resistance decreases, but buffer zones prevent forming large TSVs
Solution Approach 1:
The patent merges multiple closely located TSVs into a single larger TSV structure. By combining several small TSVs that would individually be constrained by buffer zone limitations, the invention creates a large effective TSV cross-section that reduces resistance while still fitting within the original buffer zone boundaries. This merging approach allows the TSV to achieve lower resistance without requiring additional lateral space that would violate buffer zone requirements.
2Ease of operation
If multiple small TSVs are used instead of merging, then buffer zone requirements are met, but resistance increases
Solution Approach 1:
The patent applies merging by consolidating multiple small TSV structures into one larger TSV. The multiple small TSVs that would individually comply with buffer zone requirements are combined to form a single large TSV that maintains layout compliance while achieving lower resistance through increased cross-sectional area. This resolves the contradiction by showing that merging can simultaneously satisfy buffer zone constraints and reduce resistance.
Data Source
AI summary
A method includes finding a first plurality of through-silicon vias from a first layout of a wafer, and finding a second plurality of through-silicon vias from the first plurality of through-silicon vias. The second plurality of through-silicon vias are connected in parallel. The second plurality of through-silicon vias are merged into a large through-silicon via to generate a second layout of the wafer.