Merged Write Driver for Memory Device Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face inefficiencies in writing data due to the distribution of write voltages across multiple write circuits, leading to variations in voltage levels at merged nodes, which can affect data storage reliability and operational efficiency.
Innovation Solution
A memory device with a merged write driver that receives n-bit data and outputs specific write voltages to merged nodes, utilizing column multiplexers to apply these voltages to corresponding memory cells, thereby minimizing voltage distribution variations and optimizing data storage across sub-memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple write circuits are used to write data to different sub-memory cell arrays, then data storage capacity is increased, but voltage distribution variations occur leading to reduced reliability
Solution Approach 1:
The patent merges multiple write circuits into a single unified write circuit that can selectively output write voltages to different sub-memory cell arrays. This consolidation eliminates voltage distribution variations caused by multiple separate circuits while maintaining the ability to store data across multiple sub-memory cell arrays, thus resolving the contradiction between increased storage capacity and reduced reliability.
2Productivity
If multiple write circuits are distributed across the memory device, then write operations can be performed in parallel, but the area required for write circuit integration increases
Solution Approach 1:
The patent combines multiple write circuits into one unified write circuit, significantly reducing the area required for write circuit integration. The unified circuit maintains the capability to perform write operations across multiple sub-memory cell arrays by selectively outputting voltages, thus achieving area reduction while preserving operational efficiency.
Solution Approach 2:
The unified write circuit is designed to be multi-functional, capable of selectively writing data to different sub-memory cell arrays. This universal design allows a single circuit to replace multiple dedicated circuits, reducing overall area while maintaining the ability to perform parallel write operations across different memory regions.
3Productivity
If write voltages are distributed across multiple merged nodes, then data can be written to multiple memory cells simultaneously, but voltage level variations affect operational efficiency
Solution Approach 1:
The patent merges multiple merged nodes into a single unified merged node that serves all sub-memory cell arrays. This unification ensures that the same write voltage is applied to all memory cells being written to simultaneously, eliminating voltage level variations while maintaining the ability to perform parallel write operations across multiple memory cells.
Data Source
AI summary
A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ≥2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.