Merging Design Constraint Files for IC Verification
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Solution Overview
Problem
The existing design constraint modeling process, particularly using multiple Synopsys Design Constraints (SDC) files, is time-consuming and error-prone due to conflicting requirements across different operational modes, necessitating a more efficient and comprehensive solution for integrated circuit design verification.
Innovation Solution
A method for merging multiple design constraints files into a single, pessimistic merged file using a merging rule, allowing for verification of integrated circuit designs across all operational modes with a single run, thereby reducing errors and optimizing design validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple SDC files are used for different operational modes, then each mode can be optimized with specific constraints, but the verification process becomes time-consuming and error-prone
Solution Approach 1:
The patent merges multiple operational mode SDC files into a single merged SDC file that contains timing constraints for all operational modes. This consolidation eliminates the need to separately process and verify each mode's constraints, reducing verification time while maintaining comprehensive constraint coverage through the pessimistic merging approach.
2Adaptability or versatility
If multiple SDC files are used for different operational modes, then mode-specific optimization is possible, but conflicts between constraints increase errors
Solution Approach 1:
The patent applies local quality by selectively extracting and applying only the relevant timing constraints from each operational mode's SDC file based on the current verification context. The pessimistic merging approach ensures that for each timing path, the most restrictive constraint across all modes is applied, maintaining constraint consistency while preserving mode-specific optimization capabilities.
3Reliability
If multiple runs are performed for different operational modes, then comprehensive verification is achieved, but productivity decreases
Solution Approach 1:
The patent creates a universal merged SDC file that serves all operational modes simultaneously. This single consolidated constraint file can be used for verifying the entire design across all modes in one run, eliminating the need for multiple separate verification passes and significantly improving design verification throughput while maintaining completeness.
4Measurement precision
If multiple SDC files are managed separately, then mode-specific constraints are precise, but device complexity increases
Solution Approach 1:
The patent merges multiple SDC files into a single consolidated file that maintains the precision of mode-specific constraints through the pessimistic merging approach. This unified file structure simplifies constraint management by eliminating the need to handle multiple separate files, reduce conflicts, and coordinate verification across multiple modes, thereby reducing device complexity while preserving constraint precision.
Data Source
AI summary
In the field of integrated circuit (IC) design it is common to use a plurality of design constraints files to provide the appropriate operational mode when checking the design. Designers typically use the Synopsis® design constraint (SDC) format to describe the constraints in each operational mode. Each time an operational mode is tested a corresponding SDC is used. By merging a plurality of SDCs into a single most pessimistic SDC, designers are able to ensure that the device will properly operate in all the defined operational modes. Only a single run of the merged SDC in the hypothetical mode is required thereby saving time as well as avoiding potential errors from conflicting constraints in different operational modes.