Merging Predicated Instruction Pipeline Timing

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Solution Overview

Problem

In data processing pipelines, predicated instructions face challenges in efficiently merging results with previous register values due to timing issues, leading to potential delays in forwarding merged results to subsequent instructions.

Innovation Solution

The processing pipeline is configured to permit the issuance of merging predicated instructions even when the destination register is unavailable at the stage where the processing result is determined, allowing the merging operation to be performed at a later stage, thereby enabling earlier issuance of independent instructions and reducing pipeline bubbles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the merging predicated instruction is issued only when the destination register is available at the pipeline stage where the processing result is determined, then the merging operation can be performed immediately, but independent instructions are delayed and pipeline bubbles increase

Engineering Contradiction:
Improveaverage performance per instructionVSAvoiddelay in forwarding merged results
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The processing pipeline determines the processing result earlier than the destination register becomes available, and prepares the merging operation in advance. The issue control circuitry allows the merging predicated instruction to be issued before the destination register value is ready, so that when the register becomes available, the merging can be performed immediately without delaying independent instructions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The pipeline stage at which the merging operation is performed is made dynamic rather than fixed. The merging operation can be performed at the original pipeline stage if the destination register is available, or at a later pipeline stage if the register becomes available later. This flexibility allows the system to optimize for overall throughput rather than strict timing at a single stage.

Inventive Principle:
Principle #15Dynamics

2Reliability

If the merging operation waits for the destination register to be available, then data correctness is ensured, but pipeline throughput decreases due to instruction delays

Engineering Contradiction:
Improvedata correctnessVSAvoidpipeline throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The issue control circuitry acts as an intermediary that decouples the instruction issuance timing from the register availability timing. It allows the merging predicated instruction to be issued and processed even though the destination register value is not yet available, using placeholder or temporary storage mechanisms that ensure correctness when the actual value becomes available.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If independent instructions are held back to maintain proper merging timing, then merging accuracy is preserved, but overall instruction execution speed decreases

Engineering Contradiction:
Improvemerging accuracyVSAvoidinstruction execution speed
Core Design Contradiction:
Manufacturing precisionVSSpeed

Solution Approach 1:

The processing pipeline is segmented into independent stages that can operate autonomously. The determination of the processing result is separated from the merging operation, allowing the result to be determined in one pipeline stage while the merging occurs in a subsequent stage when the destination register is available. This segmentation allows independent instructions to proceed without waiting for the merging to complete.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11036510B2Processing merging predicated instruction with timing permitting previous value of destination register to be unavailable when the merging predicated instruction is at a given pipeline stage at which a processing result is determined
Publication Date: 2021.06.15 ARM LTD
  • US11036510B2 patent drawing
  • US11036510B2 patent drawing
  • US11036510B2 patent drawing

AI summary

A merging predicated instruction controls a processing pipeline to perform a processing operation to determine a processing result based on at least one source operand, and to perform a merging operation to merge the processing result with a previous value of a destination register under control of a predicate value identifying, for each of a plurality of portions of the destination register, whether that portion is to be set to a corresponding portion of the processing result or a corresponding portion of the previous value. The merging predicated instruction is permitted to be issued to the pipeline with a timing which results in the previous value of the destination register still being unavailable when the merging predicated instruction is at a given pipeline stage at which the processing result is determined. This can help to improve performance of subsequent instructions which are independent of the merging predicated instruction.