Merging Unit FPGA PHY Prioritizes IEEE 1588 Packets
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Solution Overview
Problem
Existing Merging Units in substation automation systems require dedicated interfaces for system configuration, testing, and online diagnosis, which increase costs, and IEEE 1588 synchronization over fiber links often share Ethernet ports but lack efficient prioritization of communication loads.
Innovation Solution
Implementing a Merging Unit with a single Ethernet fiber link that shares IEEE 1588 communication for time synchronization, system configuration, and online diagnosis, using a FPGA-based PHY with two MACs and FIFO buffers to prioritize IEEE 1588 packets, and an embedded web server for user interaction, reducing hardware complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated Ethernet fiber interface is used for system configuration, testing and online diagnosis, then communication reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines multiple communication functions (sampling measurement values transmission, IEEE 1588 time synchronization, and system configuration/testing/diagnosis) into a single shared Ethernet fiber interface. The PHY layer is shared across multiple MAC layers, eliminating the need for separate dedicated interfaces and reducing hardware complexity while maintaining communication reliability through protocol-level prioritization.
Solution Approach 2:
The Ethernet fiber interface is designed to serve multiple functions simultaneously: transmitting sampling measurement values, receiving IEEE 1588 synchronization packets, and handling system configuration/testing/diagnosis traffic. This multi-functional design reduces the number of required interfaces and associated hardware components.
2Device complexity
If IEEE 1588 communication shares an Ethernet port with other communications, then device complexity is reduced, but time synchronization precision deteriorates due to communication conflicts
Solution Approach 1:
The patent implements dynamic packet prioritization at the PHY layer, where IEEE 1588 synchronization packets are assigned higher priority than sampling measurement values. The PHY layer dynamically identifies and prioritizes IEEE 1588 packets, ensuring they are transmitted first when conflicts occur, thereby maintaining time synchronization precision even with shared interface usage.
Solution Approach 2:
The PHY layer acts as an intermediary between the Ethernet fiber interface and multiple MAC layers. It mediates packet transmission by implementing prioritization logic that ensures IEEE 1588 packets receive preferential treatment, resolving conflicts between different communication functions and maintaining synchronization precision.
3Quantity of substance
If a single shared Ethernet fiber link is used for multiple functions, then material costs are reduced, but communication efficiency deteriorates due to packet prioritization requirements
Solution Approach 1:
The system implements dynamic prioritization where IEEE 1588 packets are automatically identified and given transmission priority over sampling measurement values. This dynamic packet handling mechanism maintains high communication efficiency by ensuring critical synchronization traffic is transmitted first, preventing delays that would compromise time synchronization accuracy.
Solution Approach 2:
The patent replaces physical separation of communication channels (mechanical/system-level separation) with protocol-level prioritization mechanisms. Instead of using separate dedicated interfaces, the system uses intelligent packet prioritization at the PHY and MAC layers to manage traffic, achieving similar isolation and efficiency effects through software/firmware control rather than hardware separation.
Data Source
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AI summary
The present invention is directed towards a merging unit comprising a first medium access controller(MAC), a second medium access controller, a physical layer transceiver (PHY) and an Ethernet port, wherein the first MAC is adapted to identify and forward packets for time synchronism, and the PHY is adapted to forward data received from the Ethernet port to the first MAC and the second MAC, and to transmit through the Ethernet port, packets from the first MAC and/or the second MAC. The packets from the first MAC have higher priority than the packets from the second MAC. The first MAC, and the PHY are implemented in a FPGA chip. In the merging unit, a single Ethernet fiber link may be shared for time synchronization and MU system configuration, testing and/or online diagnosis, while ±1 us time synchronization precision is guaranteed.