Trench Gate MOSFET Mesa Buffer for Withstand Voltage
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Solution Overview
Problem
Trench gate power MOSFETs face challenges in securing sufficient withstand voltage due to depletion layer penetration between trenches, leading to potential electric field concentration and breakdown issues.
Innovation Solution
The semiconductor device design includes trenches with insulators and field plates, where the mesa portion is electrically coupled to the semiconductor region, and the absence of a gate electrode at the upper part of certain trenches helps maintain a distance between the depletion layer and the gate electrode, reducing electric field concentration and enhancing withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If trenches are arranged closely in the active region to increase device density, then productivity and area utilization are improved, but the distance between adjacent trenches is reduced causing depletion layer penetration and insufficient withstand voltage
Solution Approach 1:
A mesa portion (semiconductor region of second conductivity type) is introduced as an intermediary structure between adjacent trenches in the active region. This mesa portion acts as a buffer that prevents direct depletion layer penetration between trenches while maintaining close spacing for high device density. The mesa portion is electrically coupled to the main electrode and positioned between the first and second trenches, creating an intermediate zone that maintains electrical isolation.
Solution Approach 2:
The semiconductor structure is segmented into distinct regions: active regions with trenches, outer peripheral regions with trenches, and mesa portions separating them. This segmentation allows independent optimization of each region - trenches can be closely spaced in active regions for high density while mesa portions provide necessary isolation zones, resolving the contradiction between density and withstand voltage.
2Area of stationary object
If a gate electrode is positioned at the upper part of every trench to maximize active area, then device area utilization is improved, but electric field concentration occurs at the gate electrode-depletion layer interface reducing reliability
Solution Approach 1:
Different trench configurations are applied to different regions: trenches in the active region have gate electrodes at the upper part to maximize active area, while trenches in the outer peripheral region lack gate electrodes at the upper part to prevent electric field concentration. This local differentiation allows each region to be optimized for its specific function without compromising overall device performance.
3Quantity of substance
If the depletion layer penetrates between trenches to reduce on-resistance, then electrical conductivity is improved, but the distance to gate electrode is reduced causing breakdown risks
Solution Approach 1:
The mesa portion serves as an intermediary semiconductor region that allows controlled depletion layer extension while preventing direct contact between the depletion layer and gate electrodes in adjacent trenches. The mesa portion is doped with the second conductivity type and is positioned between trenches, creating a buffer zone that maintains sufficient safety distance for gate electrode operation while still allowing low on-resistance through controlled depletion penetration in the active regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses electric field concentration and improves withstand voltage by ensuring a sufficient distance between the depletion layer and the gate electrode, thereby enhancing the semiconductor device's reliability in high-voltage applications.
Implementation Method 1
each trench comprising an insulator positioned inside the trench, a gate electrode positioned at an upper part in the insulator, and a first field plate positioned at a lower part in the insulator
Implementation Method 2
a depletion layer located below the outermost region to be coupled to a source electrode
Data Source
AI summary
A semiconductor device is disclosed that includes a group of trenches positioned in active region inside a first semiconductor region. A first trench is positioned in an outer peripheral region on an outer side of an active region. A second trench is positioned on an outer side of the first trench positioned in the outer peripheral region on the outer side of the active region. A mesa portion is positioned between the first and the second trenches. An insulating layer is positioned inside the first and second trenches. A second field plate is positioned inside the insulating layer in the first trench. A third field plate positioned inside the second insulating layer in the second trench. The mesa portion includes the semiconductor region electrically coupled to the first main electrode on an outermost side. The first trench does not have the gate electrode at upper part of the first trench.