Mesa and Fin Isolation Layout for Stable Planar Capacitance
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Solution Overview
Problem
The integration of manufacturing methods for fin devices and other devices in semiconductor integrated circuits poses challenges in meeting product specifications, particularly in terms of electrical performance and device density.
Innovation Solution
A semiconductor device and manufacturing method that include a mesa structure in the planar device region and fin-shaped structures in the fin device region, with an isolation structure covering the sidewall of the mesa structure and an electrically conductive structure extending above the isolation structure to improve electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the electrically conductive structure is extended to be located above the isolation structure, then the electrical performance of the planar device is improved, but the device complexity increases
Solution Approach 1:
The electrically conductive structure extends into the vertical dimension by being positioned above the isolation structure, rather than only in the horizontal plane. This vertical extension increases the overlap area with the mesa structure, thereby improving electrical performance (capacitance stability) while utilizing the third dimension to resolve the contradiction.
Solution Approach 2:
The isolation structure serves as an intermediary element that enables the electrically conductive structure to extend above it without directly contacting the mesa structure sidewall. This intermediary positioning allows the conductive structure to improve electrical performance while the isolation structure maintains proper electrical isolation and structural support.
2Reliability
If the isolation structure covers the sidewall of the mesa structure, then the electrical performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The isolation structure is segmented into two distinct portions: a first portion that covers the sidewall of the mesa structure and a second portion that is positioned between fin-shaped structures. This segmentation allows each portion to be optimized for its specific function, with the first portion providing sidewall coverage for electrical performance while the second portion provides isolation between fins.
Solution Approach 2:
Different portions of the isolation structure have different heights and positions tailored to local requirements. The first portion extends higher to cover the mesa sidewall, while the second portion is positioned differently to isolate fin structures. This local differentiation optimizes electrical performance without requiring uniform high-precision manufacturing across the entire structure.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, an isolation structure, and a first electrically conductive structure. The semiconductor substrate has a planar device region and a fin device region. The semiconductor substrate includes a mesa structure disposed in the planar device region and fin-shaped structures disposed in the fin device region. The isolation structure is disposed on the semiconductor substrate and includes a first portion which is disposed on the planar device region and covers a sidewall of the mesa structure, and the isolation structure further includes a second portion which is disposed on the fin device region and located between the fin-shaped structures. The first electrically conductive structure is disposed on the planar device region. The first electrically conductive structure is partly disposed above the mesa structure in a vertical direction and partly disposed above the first portion of the isolation structure in the vertical direction.