GAA Gate Spacer Mesa Profile to Prevent Gate-Source/Drain Shorts
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Solution Overview
Problem
Existing semiconductor technologies face challenges in forming non-planar transistor devices, particularly in the formation of active gate structures, where the etch stop layer's removal can lead to short circuits between the gate and source/drain structures.
Innovation Solution
The method involves forming a gate-all-around (GAA) FET device by patterning an etch stop layer through a dummy gate structure, which creates a mesa-like profile. This profile allows the gate spacer to form a tilted portion, effectively isolating the etch stop layer and preventing short circuits during the formation of the active gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the etch stop layer is removed during the formation of active gate structure, then the manufacturing process is simplified, but short circuits between gate and source/drain structures occur
Solution Approach 1:
The etch stop layer is patterned to create a mesa-like profile with exposed sidewalls before the active gate structure is formed. This preliminary action allows the gate spacer to be deposited conformally on the exposed sidewalls, creating electrical isolation before the active gate structure is formed, thus preventing short circuits while maintaining process simplicity
Solution Approach 2:
The gate spacer acts as an intermediary layer between the etch stop layer and the active gate structure. By depositing the gate spacer on the exposed sidewalls of the patterned etch stop layer, electrical isolation is achieved without requiring complete removal of the etch stop layer, thus preventing short circuits while maintaining process simplicity
2Reliability
If the etch stop layer is kept intact during dummy gate formation, then electrical isolation is maintained, but the process window for forming active gate structure is reduced
Solution Approach 1:
The etch stop layer is selectively patterned to expose sidewalls in advance, creating a mesa-like profile. This preliminary action enlarges the process window by providing defined geometric features that guide subsequent gate spacer deposition, while maintaining electrical isolation through the remaining etch stop layer and gate spacer structure
Solution Approach 2:
The etch stop layer is patterned to have different properties in different regions: the top surface is removed to expose sidewalls for gate spacer deposition, while portions of the etch stop layer remain to maintain electrical isolation. This local differentiation creates both the necessary geometric features and maintains reliability
Data Source
AI summary
A semiconductor device includes a plurality of semiconductor layers vertically separated from one another, a gate structure that comprises a lower portion and an upper portion, a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface, and an etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.