Mesa IGBT With Dummy Trenches For Latch-Up Suppression

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Solution Overview

Problem

Conventional semiconductor devices, such as IGBTs, face challenges in enhancing saturation current and suppressing latch-up phenomena due to limitations in carrier extraction and field crowding.

Innovation Solution

The semiconductor device incorporates a unique structure with a semiconductor substrate featuring gate trench and dummy trench portions, emitter regions, and contact regions with specific doping concentrations and orientations, along with accumulation regions, to optimize carrier flow and reduce resistance, thereby increasing saturation current and preventing latch-up.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional IGBT structures are used, then device simplicity is maintained, but saturation current is insufficient and latch-up phenomena occur

Engineering Contradiction:
Improvesaturation currentVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The device is divided into multiple functional regions including gate trench portions, dummy trench portions, mesa portions, emitter regions, contact regions, and accumulation regions. This segmentation allows each region to perform its specific function optimally, improving saturation current while managing complexity through functional specialization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions are doped with different concentrations and types of dopants. The emitter region has higher doping concentration than the drift region, while the accumulation region has even higher concentration. This local quality variation optimizes carrier extraction in specific areas to enhance saturation current

Inventive Principle:
Principle #3Local quality

2Reliability

If carrier extraction is not optimized, then device structure remains simple, but latch-up phenomena occur and performance deteriorates

Engineering Contradiction:
Improvelatch-up suppressionVSAvoidcarrier extraction structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Accumulation regions are formed in advance within the drift region to pre-position carrier storage zones. These regions are created before final device operation, enabling efficient carrier extraction during normal operation and preventing latch-up phenomena

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The accumulation regions act as intermediary structures between the emitter region and the drift region, facilitating smooth carrier transport and extraction. This intermediary structure prevents direct harmful interactions that could cause latch-up while maintaining efficient current flow

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances saturation current density and suppresses latch-up by efficiently extracting carriers and managing electric field distribution, leading to improved performance and reliability of the semiconductor device.

Implementation Method 1

a first conductivity-type emitter region that is provided inside the mesa portion and between the upper surface of the semiconductor substrate and the drift region, is provided at an upper surface of the mesa portion and adjacent to the gate trench portion and has a doping concentration higher than that of the drift region

Methodology Applied
Scientific EffectDoping: Dopants

Implementation Method 2

This configuration enhances saturation current density and suppresses latch-up by efficiently extracting carriers and managing electric field distribution

Methodology Applied
Scientific EffectElectric field distribution: Electric Field

Data Source

PatentUS10600867B2Semiconductor device having an emitter region and a contact region inside a mesa portion
Publication Date: 2020.03.24 FUJI ELECTRIC CO LTD
  • US10600867B2 patent drawing
  • US10600867B2 patent drawing
  • US10600867B2 patent drawing

AI summary

A semiconductor device includes: a gate trench portion and a dummy trench portion provided extending in a predetermined direction of extension at the upper surface of the semiconductor substrate; a mesa portion sandwiched by the gate trench portion and the dummy trench portion; an emitter region provided between the upper surface of the semiconductor substrate and the drift region and provided at an upper surface of the mesa portion and adjacent to the gate trench portion; and a contact region provided between the upper surface of the semiconductor substrate and the drift region and provided at the upper surface of the mesa portion and adjacent to the dummy trench portion.