Semiconductor Mesa Transistor Base Contact Cavity

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Solution Overview

Problem

Existing semiconductor devices with bipolar transistors and field effect transistors have high-frequency characteristics that need improvement and complex manufacturing processes, with challenges in controlling base contact and reducing parasitic components.

Innovation Solution

Incorporating self-aligned insulation-filled cavities in the collector region of the bipolar transistor to define the base contact and reduce base-collector capacitance, achieved by selectively etching polysilicon towards monocrystalline regions and filling the cavities with silicon dioxide or gas, such as air.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If self-aligned insulation-filled cavities are incorporated to reduce base-collector capacitance and define base contact, then high-frequency characteristics are improved, but manufacturing complexity increases

Engineering Contradiction:
Improvehigh-frequency characteristicsVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating layer is deposited over the entire surface before the cavity formation steps, preparing the structure in advance. The selective etching process then reveals the insulating layer in specific regions to form cavities, eliminating the need for separate cavity isolation steps and simplifying the overall manufacturing process while achieving the desired base contact definition and capacitance reduction.

Inventive Principle:
Principle #10Preliminary action

2Object-generated harmful factors

If dummy emitter is used to etch away parasitic components, then parasitic components are reduced, but control of base contact becomes difficult

Engineering Contradiction:
Improveparasitic componentsVSAvoidbase contact control
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The insulating layer acts as an intermediary element that enables precise control of the base contact. By selectively removing portions of this pre-deposited insulating layer through the access paths, the base contact geometry is precisely defined without relying on dummy emitters, thereby maintaining manufacturing precision while still achieving parasitic component reduction.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If conventional isolation methods are used surrounding the mesa, then device structure is simplified, but base-collector capacitance cannot be effectively reduced

Engineering Contradiction:
Improvedevice structureVSAvoidbase-collector capacitance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The insulating layer is applied uniformly across the entire surface, but through selective etching, local regions are exposed to form cavities. This creates localized insulating regions precisely where needed - surrounding the mesa for structural isolation and within the collector region for capacitance reduction - while maintaining a simple overall device structure without complex multi-layer isolation schemes.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces parasitic components and improves high-frequency characteristics by defining the base contact and minimizing base-collector capacitance, simplifying the manufacturing process and enhancing device performance.

Implementation Method 1

reduce the base-collector capacitance

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

selectively etching polysilicon towards monocrystalline regions

Methodology Applied
Scientific EffectEtching:

Implementation Method 3

filling the cavities with silicon dioxide or gas, such as air

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS8476675B2Semiconductor device and method of manufacture thereof
Publication Date: 2013.07.02 NXP BV
  • US8476675B2 patent drawing
  • US8476675B2 patent drawing
  • US8476675B2 patent drawing

AI summary

A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.