Mesa-Structured III-V Wafer Layout for Low-Resistance Power Transistors
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Solution Overview
Problem
Existing transistors used in power electronic applications, such as Si CoolMOS, Si Power MOSFETs, and Si IGBTs, have limitations in terms of current carrying capacity, voltage support, on-resistance, and switching speed, which are not adequately addressed by silicon carbide or gallium nitride devices.
Innovation Solution
A method for fabricating a semiconductor wafer involves epitaxially growing a III-V semiconductor on a foreign wafer, forming mesas, applying an insulation layer, and progressively removing the wafer's second surface to expose the insulation layer, thereby creating a structured surface for improved transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon carbide or gallium nitride devices are used to improve current carrying capacity and switching speed, then electrical performance is enhanced, but manufacturing complexity and device structure complexity increase
Solution Approach 1:
The device is segmented into distinct functional regions including mesas separated by insulating regions, with the active semiconductor material divided into discrete islands on a carrier substrate. This segmentation enables independent optimization of each region while managing overall device complexity.
Solution Approach 2:
A carrier substrate is introduced as an intermediary element that supports the III-V semiconductor material during fabrication and operation. This mediator allows the use of complex III-V materials while providing a manageable platform for device construction and thermal management.
2Reliability
If epitaxial growth on foreign wafer is used to achieve improved transistor performance, then electrical characteristics are enhanced, but manufacturing process complexity increases
Solution Approach 1:
The carrier substrate is prepared in advance with appropriate surface treatments and structural configurations before epitaxial growth. This preliminary preparation simplifies the subsequent growth process and enables better control over the III-V semiconductor layer formation.
Solution Approach 2:
The foreign wafer serves as an intermediary platform that enables epitaxial growth of III-V materials with different crystal structures. This mediator substrate allows lattice mismatch management and provides a stable foundation for high-performance transistor fabrication.
3Reliability
If mesas are formed with insulation layers to reduce on-resistance, then electrical resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Insulating regions are selectively applied in specific locations between mesas rather than uniformly across the entire substrate. This localized approach reduces on-resistance in critical areas while maintaining manufacturing feasibility and reducing overall precision requirements.
Solution Approach 2:
Material is selectively removed to form mesas with insulating regions between them, extracting only the necessary conductive paths while leaving insulating barriers in place. This selective extraction approach simplifies the formation process compared to attempting to build up complex three-dimensional structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor devices with enhanced current handling, voltage support, reduced on-resistance, and faster switching times, addressing the limitations of existing power electronic transistors.
Implementation Method 1
epitaxially growing a III-V semiconductor on a first surface of a foreign wafer
Data Source
AI summary
A semiconductor device includes a plurality of mesas, each mesa including an epitaxial Group III nitride-based multi-layer structure, an insulating matrix having an upper surface and a lower surface, wherein side faces of the mesas are embedded in the insulating matrix and a top surface of the mesas is substantially coplanar with the upper surface of the insulating matrix, and a metallization structure including a gate finger and a drain finger arranged on the top surface of each mesa, a drain bus that electrically couples a first drain finger arranged on a first mesa with a second drain finger arranged on a second mesa, and a gate bus that electrically couples a first gate finger arranged on the first mesa with a second gate finger arranged on a second mesa.