Mesa Width Precision in Semiconductor Transistor Patterning
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Solution Overview
Problem
Existing methods for forming mesa structures in semiconductor devices, such as IGBTs, face challenges in defining these structures with precise and uniform width, which is crucial for enhancing the performance of power semiconductor devices.
Innovation Solution
A method involving the formation of a sacrificial layer, patterning, spacer formation, and etching to create trenches and mesas in a semiconductor substrate, allowing for the precise definition of mesa widths between 50 to 500 nm, enabling the homogeneous patterning of mesa structures across a large area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional direct patterning methods are used to define mesa structures, then the manufacturing process is simple, but the manufacturing precision of mesa width is insufficient and cannot achieve homogeneous widths of 50 to 500 nm
Solution Approach 1:
The patterning process is segmented into multiple independent steps: forming a sacrificial layer, depositing a first spacer layer to define initial dimensions, forming a second spacer layer for final precision, and selective removal. This segmentation allows each step to be optimized independently, achieving the required 50-500 nm mesa width precision that cannot be achieved through single-step direct patterning.
Solution Approach 2:
The sacrificial layer is formed in advance before the actual mesa structure definition. This preliminary layer serves as a template that guides subsequent spacer formation and material deposition, ensuring homogeneous mesa widths are achieved before the final structure is created. The preliminary action enables precise dimensional control that would be difficult to achieve through direct patterning alone.
2Productivity
If mesa width is reduced to enhance IGBT performance, then the current capacity and performance increase, but the uniformity and precision of mesa structures become difficult to maintain
Solution Approach 1:
The sacrificial layer acts as an intermediary element that enables precise mesa width definition. By using this temporary structure as a template, the method achieves homogeneous mesa widths of 50-500 nm that would be difficult to obtain through direct patterning. The intermediary allows the final structure to be defined with high precision while maintaining uniformity across the substrate.
Solution Approach 2:
The method uses parameter changes in the spacer layer thicknesses to precisely control mesa width. By adjusting the thickness of the first and second spacer layers, the mesa width can be precisely controlled within the 50-500 nm range. This parameter-based control ensures both the reduced width needed for high performance and the uniformity required for manufacturing consistency.
3Loss of time
If direct etching without sacrificial layer is used, then the manufacturing process is faster, but the homogeneous definition of small mesa widths cannot be achieved
Solution Approach 1:
The sacrificial layer and spacer structures are formed in advance as preliminary templates before the actual mesa etching. This preliminary action, while adding steps to the process, ensures that the subsequent etching produces homogeneous mesa widths with high precision. The time invested in preliminary structure formation is necessary to achieve the required 50-500 nm width uniformity that direct etching cannot provide.
Solution Approach 2:
The sacrificial layer serves as an intermediary template that guides the formation of homogeneous mesa structures. This intermediary structure enables precise width definition during etching, ensuring uniformity across the substrate. The presence of this intermediary, while extending manufacturing time, is essential for achieving the precision and homogeneity required for high-performance IGBTs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the homogeneous definition of mesa widths, enhancing the performance of semiconductor devices by improving the uniformity and precision of mesa structures, thereby increasing the performance and current capacity of IGBTs.
Implementation Method 1
etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate
Data Source
AI summary
A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.