MESFET Buried P-Type Gate for Low On-Resistance
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Solution Overview
Problem
High power and high frequency electrical circuits require transistors that can handle increased power loads while maintaining reliable operation at radio frequencies, but existing transistors face challenges in reducing on-resistance without increasing input-output capacitance.
Innovation Solution
A metal-semiconductor field-effect transistor (MESFET) design with a p-type conductivity region beneath the gate between the source and drain, electrically coupled to the gate, allowing for a thicker n-type conductivity channel layer that reduces on-resistance without significantly increasing input-output capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the n-type conductivity channel layer thickness is increased to reduce on-resistance, then the on-resistance decreases, but the input-output capacitance increases
Solution Approach 1:
The invention divides the gate control into two independent parts: the primary gate on the n-type channel layer and a secondary p-type conductivity region beneath the gate. This segmentation allows independent optimization of the channel layer thickness for low on-resistance while the p-type region compensates for increased capacitance through electrostatic control, resolving the trade-off between resistance and capacitance.
Solution Approach 2:
The p-type conductivity region acts as an intermediary element that mediates between the gate and the substrate. It provides electrostatic control over the channel while allowing the channel layer to be thicker for reduced on-resistance. The p-type region compensates for the increased capacitance by providing additional electrostatic control, enabling thicker channels without proportionally increasing effective capacitance.
2Power
If the channel layer thickness is increased to improve power handling, then power handling capability increases, but device control becomes more difficult
Solution Approach 1:
By segmenting the gate control into a primary gate and a secondary p-type region, the invention enables thick channel layers for high power handling while maintaining effective control. The p-type region provides additional electrostatic control that compensates for the increased distance and reduced gate control efficiency associated with thicker channels.
Data Source
AI summary
A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.