Configurable Mesh Data Bus for Parallel Transactional Memory Access

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Solution Overview

Problem

Existing network processors face challenges in efficiently handling packet traffic due to limitations in inter-island communication and resource management, leading to suboptimal performance and scalability.

Innovation Solution

The introduction of a configurable mesh data bus and distributed credit FIFO structure in an island-based network flow processor (IB-NFP) integrated circuit, which enables simultaneous communication across multiple islands and dynamic resource allocation through a staggered island layout and shared memory interface, enhancing inter-island connectivity and resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a traditional bus architecture is used for inter-island communication, then the device complexity is reduced, but the productivity and packet processing efficiency deteriorate due to limited simultaneous operations

Engineering Contradiction:

Improvepacket processing efficiencyVSAvoidmesh data bus configuration

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system is divided into multiple independent islands, each with its own functional circuitry and local memory. The mesh data bus is segmented into multiple independent channels that can operate simultaneously, allowing parallel communication between different island pairs without interference

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The interconnect architecture transitions from a traditional one-dimensional bus to a two-dimensional mesh topology. This dimensional change enables multiple communication paths and simultaneous operations, fundamentally increasing the system's throughput capability while maintaining manageable complexity through modular design

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Loss of time

If islands are arranged in a non-staggered layout, then the manufacturing precision requirements are reduced, but the loss of time increases due to longer communication paths between islands

Engineering Contradiction:

Improvecommunication latencyVSAvoidisland positioning accuracy

Core Design Contradiction:

Loss of timeVSManufacturing precision

Solution Approach 1:

The islands are arranged in an asymmetric staggered pattern rather than a symmetric grid. This asymmetric layout optimizes communication paths by positioning islands to minimize average distance while maintaining ease of manufacturing through standardized half-link interfaces that accommodate the staggered arrangement

Inventive Principle:

Principle #4Asymmetry

3Adaptability or versatility

If fixed functional circuits are assigned to specific islands, then the ease of manufacture is improved, but the adaptability deteriorates as processing requirements change

Engineering Contradiction:

Improvefunctional circuit configurabilityVSAvoidisland fabrication complexity

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The system transitions from static fixed assignments to dynamic reconfigurability. Each island contains functional circuitry that can be programmed or configured at runtime, allowing the same physical island to perform different functions based on processing requirements while maintaining a standardized manufacturing process

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Islands are designed with universal interfaces and standardized half-link connections that enable them to serve multiple functions. The mesh data bus provides universal access to all islands, allowing any island to communicate with any other island for any operation type, maximizing system versatility

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Productivity

If simultaneous read/write operations are enabled across multiple islands, then the productivity increases, but the reliability may worsen due to potential conflicts and errors

Engineering Contradiction:

Improvesimultaneous operation throughputVSAvoiddata bus transaction accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The mesh data bus includes intermediary control mechanisms such as arbitration logic and protocol handlers that mediate between simultaneous read/write requests from different islands. These intermediaries coordinate access to prevent conflicts, ensure data integrity, and maintain reliability while allowing high throughput parallel operations

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUSRE50677E1Configuration mesh data bus and transactional memories in a multi-processor integrated circuit

Publication Date: 2025.11.25 NETRONOME SYSTEMS INC

AI summary

A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.